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| 型號： | TMS320C242FNA |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 18/66頁 |
| 文件大小： | 803K |
| 代理商： | TMS320C242FNA |
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TMS320C242
DSP CONTROLLER
SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupt request structure
1.
At the lower level of the hierarchy, the peripheral interrupt requests (PIRQs) from several peripherals to the
interrupt controller are ORed together to generate a request to the CPU. There is an interrupt flag bit and
an interrupt enable bit located in the peripheral for each event that can cause a peripheral interrupt request.
There is also one PIRQ for each event. If an interrupt-causing event occurs in a peripheral, and the
corresponding interrupt enable bit is set, the interrupt request from the peripheral to the interrupt controller
is asserted. This interrupt request simply reflects the status of the peripheral’s interrupt flag gated with the
interrupt enable bit. When the interrupt flag is cleared, the interrupt request is cleared. Some peripherals
have the capability to make either a high-priority or a low-priority interrupt request. If a peripheral has this
capability, the value of its interrupt priority bit is transmitted to the interrupt controller. The interrupt request
continues to be asserted until it is either automatically cleared by an interrupt acknowledge or cleared by
software.
2.
At the upper level of the hierarchy, the ORed PIRQs generate interrupt (INT) requests to the CPU. The
request to the ’24x CPU is a low-going pulse of 2 CPU clock cycles. The Peripheral Interrupt Expansion
(PIE) controller generates an INT pulse when any of the PIRQs controlling that INT go active. If any of the
PIRQs capable of asserting that CPU interrupt request are still active in the cycle following an interrupt
acknowledge for that INT, another INT pulse is generated in the PIE. Each INT request is followed by an
interrupt acknowledge from the CPU, which helps to clear the interrupt-causing flag in the PIE. The interrupt
controller defines which CPU interrupt requests get asserted by which peripheral interrupt requests, and
the relative priority of each peripheral interrupt request. Thus, priority is determined by the interrupt
controller and is not part of any of the peripherals. Table 5 lists interrupt source priority and vectors.
A
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PDF描述 |
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| TMS320C241 | 16-Bit Digital Signal Processor |
| TMS320C242FNS | 16-Bit Digital Signal Processor |
| TMS320C242PGA | 16-Bit Digital Signal Processor |
| TMS320C242PGS | 16-Bit Digital Signal Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TMS320C242FNS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| TMS320C242PG | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLER |
| TMS320C242PGA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| TMS320C242PGS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| TMS320C25 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SECOND-GENERATION DIGITAL SIGNAL PROCESSORS |
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