參數(shù)資料
型號(hào): TMS320C6414TZLZ7
廠商: Texas Instruments
文件頁數(shù): 19/146頁
文件大?。?/td> 0K
描述: IC DSP FIXED-POINT 532-FCBGA
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C6414T/15T/16T
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP,PCI,UTOPIA
時(shí)鐘速率: 720MHz
非易失內(nèi)存: 外部
芯片上RAM: 1.03MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 532-BFBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 532-FCBGA(23x23)
包裝: 托盤
配用: TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
其它名稱: 296-19386
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
115
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415T AND C6416T ONLY]
(CONTINUED)
timing requirements for PCI inputs (see Figure 49)
NO.
600
720
850
1G
UNIT
MIN
MAX
5
tsu(IV-PCLKH)
Setup time, input valid before PCLK high
7
ns
6
th(IV-PCLKH)
Hold time, input valid after PCLK high
0
ns
switching characteristics over recommended operating conditions for PCI outputs (see Figure 49)
NO.
PARAMETER
600
720
850
1G
UNIT
MIN
MAX
1
td(PCLKH-OV)
Delay time, PCLK high to output valid
11
ns
2
td(PCLKH-OIV)
Delay time, PCLK high to output invalid
2
ns
3
td(PCLKH-OLZ)
Delay time, PCLK high to output low impedance
2
ns
4
td(PCLKH-OHZ)
Delay time, PCLK high to output high impedance
28
ns
Valid
PCLK
5
PCI Output
PCI Input
3
Valid
2
6
1
4
Figure 49. PCI Input/Output Timing
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