參數(shù)資料
型號(hào): TMS320C6415TBZLZA8
廠商: Texas Instruments
文件頁(yè)數(shù): 92/146頁(yè)
文件大?。?/td> 0K
描述: IC FIXED-POINT DSP 532-FCBGA
標(biāo)準(zhǔn)包裝: 60
系列: TMS320C6414T/15T/16T
類型: 定點(diǎn)
接口: 主機(jī)接口,McBSP,PCI,UTOPIA
時(shí)鐘速率: 850MHz
非易失內(nèi)存: 外部
芯片上RAM: 1.03MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 532-BFBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 532-FCBGA(23x23)
包裝: 托盤
配用: TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)當(dāng)前第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
5
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
description
The TMS320C64x
DSPs (including the TMS320C6414T, TMS320C6415T, and TMS320C6416T devices)
are the highest-performance fixed-point DSP generation in the TMS320C6000
DSP platform. The
TMS320C64x
(C64x) device is based on the second-generation high-performance, advanced VelociTI
very-long-instruction-word (VLIW) architecture (VelociTI.2
) developed by Texas Instruments (TI), making
these DSPs an excellent choice for wireless infrastructure applications. The C64x
is a code-compatible
member of the C6000
DSP platform.
With performance of up to 8000 million instructions per second (MIPS) at a clock rate of 1 GHz, the C64x devices
offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the
operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x
DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent
functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2
extensions. The VelociTI.2
extensions in the eight functional units include new instructions to accelerate the
performance in key applications and extend the parallelism of the VelociTI
architecture. The C64x can produce
four 16-bit multiply-accumulates (MACs) per cycle for a total of 4000 million MACs per second (MMACS), or
eight 8-bit MACs per cycle for a total of 8000 MMACS. The C64x DSP also has application-specific hardware
logic, on-chip memory, and additional on-chip peripherals similar to the other C6000
DSP platform devices.
The C6416T device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP)
and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The
VCP operating at CPU clock divided-by-4 can decode over 833 7.95-Kbps adaptive multi-rate (AMR) [K = 9,
R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4,
and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock
divided-by-2 can decode up to sixty 384-Kbps or ten 2-Mbps turbo encoded channels (assuming 6 iterations).
The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required
by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo
interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable.
Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.
The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The
Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit
2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is
shared between program and data space. L2 memory can be configured as mapped memory or combinations
of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial
ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM)
Slave [UTOPIA Slave] port [C6415T/C6416T only]; three 32-bit general-purpose timers; a user-configurable
16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415T/C6416T
only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory
interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and
asynchronous memories and peripherals.
The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific
enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows
debugger
interface for visibility into source code execution.
TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Other trademarks are the property of their respective owners.
Throughout the remainder of this document, the TMS320C6414T, TMS320C6415T, and TMS320C6416T shall be referred to as TMS320C64x
or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414T, C6415T, or C6416T.
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
相關(guān)PDF資料
PDF描述
TAJX157M010RNJ CAP TANT 150UF 10V 20% 2917
JWS5024/A POWER SUP 50W 24V 2.2A ENCLOSED
VE-J3D-IZ CONVERTER MOD DC/DC 85V 25W
2200LL-100-H-RC INDUCTOR TOROID 10UH 15% HORIZ
EEM06DTKH-S288 CONN EDGECARD 12POS .156 EXTEND
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320C6415TBZLZW7 制造商:Texas Instruments 功能描述:
TMS320C6415TGLZ1 制造商:Rochester Electronics LLC 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR - Bulk
TMS320C6415TGLZ6 制造商:Rochester Electronics LLC 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR - Bulk 制造商:Texas Instruments 功能描述:
TMS320C6415TGLZ7 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Fixed-Pt Dig Sig Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320C6415TGLZ8 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: