SPRS372H – MAY 2007 – REVISED APRIL 2012
6.25 IEEE 1149.1 JTAG
The JTAG (2) interface is used for BSDL testing and emulation of the device.
TRST needs to be released only when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to make certain
that TRST will always be asserted upon power up and the device's internal emulation logic will always be
properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations.
6.25.1 JTAG Peripheral Register Description(s) - JTAG ID Register
Table 6-98. JTAG ID Register
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Read-only. Provides 32-bit
0x0204 9018
JTAGID
JTAG Identification Register
JTAG ID of the device.
(2)
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. The JTAG
ID register resides at address location 0x0204 9018. The register hex value is: 0x0B77 A02F . For the
Figure 6-56. JTAGID Register (0x0204 9018)
31-28
27-12
11-1
0
VERSION
PART NUMBER (16-Bit)
MANUFACTURER (11-Bit)
LSB
R-0001
R-1011 0111 0111 1010
R-0000 0010 111
R-1
LEGEND: R = Read, W = Write, n = value at reset
Table 6-99. JTAGID Register Selection Bit Descriptions
BIT
NAME
DESCRIPTION
31:28
VERSION
Silicon version value: 0001.
27:12
PART NUMBER
Part Number (16-Bit) value: 1011 0111 0111 1010.
11-1
MANUFACTURER
Manufacturer (11-Bit) value: 0000 0010 111.
0
LSB
LSB. This bit is read as a 1.
6.25.2 JTAG Electrical Data/Timing
Table 6-100. Timing Requirements for JTAG Test Port (see Figure 6-57) 720, 800, 900, 1100
NO.
UNIT
MIN
MAX
1
tc(TCK)
Cycle time, TCK
35
ns
3
tsu(TDIV-TCKH)
Setup time, TDI/TMS/TRST valid before TCK high
2
ns
4
th(TCKH-TDIV)
Hold time, TDI/TMS/TRST valid after TCK high
0
ns
Copyright 2007–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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