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FEATURES
www.ti.com ......................................................................................................................................................... SPNS110E – AUGUST 2005 – REVISED MAY 2008
16/32-Bit RISC Flash Microcontroller
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High-Performance Static CMOS Technology
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Two Serial Communication Interfaces
(SCIs)
TMS470R1x 16/32-Bit RISC Core
(ARM7TDMI)
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224 Selectable Baud Rates
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24-MHz System Clock (48-MHz Pipeline)
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Asynchronous/Isosynchronous Modes
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Independent 16/32-Bit Instruction Set
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Two Standard CAN Controllers (SCC)
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Open Architecture With Third-Party Support
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16-Mailbox Capacity
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Built-In Debug Module
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Fully Compliant With CAN Protocol,
Version 2.0B
Integrated Memory
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Class II Serial Interface B (C2SIb)
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384K-Byte Program Flash
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Normal 10.4 Kbps and 4X Mode
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Three Banks With 18 Contiguous
41.6 Kbps
Sectors
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Three Inter-Integrated Circuit (I2C) Modules
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32K-Byte Static RAM (SRAM)
(See I2C Notes in TMS470R1A384 Silicon
Operating Features
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Core Supply Voltage (VCC): 1.71 V to 2.05 V
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Multi-Master and Slave Interfaces
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I/O Supply Voltage (VCCIO): 3.0 V to 3.6 V
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Up to 400 Kbps (Fast Mode)
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Low-Power Modes: STANDBY and HALT
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7- and 10-Bit Address Capability
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Extended Industrial Temperature Range
High-End Timer (HET)
470+ System Module
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12 Programmable I/O Channels:
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32-Bit Address Space Decoding
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12 High-Resolution Pins
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Bus Supervision for Memory/Peripherals
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High-Resolution Share Feature (XOR)
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Analog Watchdog (AWD) Timer
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High-End Timer RAM
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Enhanced Real-Time Interrupt (RTI)
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64-Instruction Capacity
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Interrupt Expansion Module (IEM)
External Clock Prescale (ECP) Module
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System Integrity and Failure Detection
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Programmable Low-Frequency External
Direct Memory Access (DMA) Controller
Clock (CLK)
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32 Control Packets and 16 Channels
12-Channel 10-Bit Multi-Buffered
Zero-Pin Phase-Locked Loop (ZPLL)-Based
Analog-to-Digital Converter (MibADC)
Clock Module With Prescaler
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32-Word FIFO Buffer
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Multiply-by-4 or -8 Internal ZPLL Option
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Single- or Continuous-Conversion Modes
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ZPLL Bypass Mode
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1.55-s Minimum Sample/Conversion Time
Expansion Bus Module (EBM) (PGE Package)
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Calibration Mode and Self-Test Features
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Supports 8- and 16-Bit Expansion Bus
55 Dedicated General-Purpose I/O (GIO) Pins
Memory Interface Mappings
and 39 Additional Peripheral I/Os (PGE)
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40 I/O Expansion Bus Pins
14 Dedicated General-Purpose I/O (GIO) Pins
Ten Communication Interfaces:
and 39 Additional Peripheral I/Os (PZ)
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Two Serial Peripheral Interfaces (SPIs)
Flexible Interrupt Handling
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255 Programmable Baud Rates
Eight External Interrupts
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
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All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 2005–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.