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參數(shù)資料
| 型號： | TMS320F206PZA |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 13/57頁 |
| 文件大?。?/td> | 793K |
| 代理商： | TMS320F206PZA |
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TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multiplier (continued)
Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the
multiplier, allowing both operands to be processed simultaneously. The data for these operations can be
transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle
multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient
addresses are generated by program address generation (PAGEN), while the data addresses are generated
by data address generation (DAGEN). This allows the repeated instruction to access the values sequentially
from the coefficient table and step through the data in any of the indirect addressing modes.
The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the
sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to
discard the oldest sample.
The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision
arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed
data memory location, with the result placed in PREG. This allows the operands of greater than 16 bits to be
broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The
SQRA (square/add) and SQRS (square/subtract) instructions pass the same value to both inputs of the
multiplier for squaring a data memory value.
After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register
(PREG). The product from PREG can be transferred to the CALU or to data memory through the SPH (store
product high) and SPL (store product low) instructions. Note: the transfer of PREG to either the CALU or data
memory passes through the PSCALE shifter and is therefore, affected by the product-shift mode value defined
by the PM bits in the ST1 register. This is important when saving PREG in an interrupt-service routine context
save as the PSCALE shift effects cannot be modeled in the restore operation. PREG can be cleared by
executing the MPY #0 instruction. The product register can be restored by loading the saved low half into TREG
and executing a MPY #1 instruction. The high half is then loaded using the LPH instruction.
central arithmetic logic unit
The TMS320F206 CALU implements a wide range of arithmetic and logical functions, the majority of which
execute in a single clock cycle. This ALU is referred to as “central” to differentiate it from a second ALU used
for indirect address generation (called the ARAU). Once an operation is performed in the CALU, the result is
transferred to the accumulator (ACC) where additional operations, such as shifting, can occur. Data that is input
to the CALU can be scaled by ISCALE when coming from one of the data buses (DRDB or PRDB) or scaled
by PSCALE when coming from the multiplier.
The CALU is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or
derived from immediate instructions. In addition to arithmetic operations, the CALU can perform Boolean
operations, facilitating the bit manipulation ability required for a high-speed controller. One input to the CALU
is always provided from the accumulator, and the other input can be provided from the product register (PREG)
of the multiplier or the output of the scaling shifter (that has been read from data memory or from the ACC). After
the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator.
The TMS320F206 supports floating-point operations for applications requiring a large dynamic range. The
NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator by
performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the
LACT/ADDT/SUBT (load/add to/subtract from accumulator with shift specified by TREG) instructions. These
instructions are useful in floating-point arithmetic where denormalization of a number is required; that is,
floating-point to fixed-point conversion. They are also useful in the implementation of automatic-gain control
(AGC) at the input of a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data
memory based on the value contained in the four LSBs of TREG.
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| TMS320F240PQ | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 32B Dig Sig Cntrllr w/ Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320F240PQA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16B 5V fixed point DSP w/ Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320F240PQG4 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC CMOS 320F240 BQFP TMS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320F240PQS | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 32B Dig Sig Cntrllr w/ Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320F241FN | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16B 5V fixed point DSP w/ Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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