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參數(shù)資料
| 型號： | TMS320F206PZA |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 9/57頁 |
| 文件大?。?/td> | 793K |
| 代理商： | TMS320F206PZA |
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TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Table 2. Legend for the ’F206 Internal Hardware Functional Block Diagram (Continued)
SYMBOL
NAME
DESCRIPTION
PM
Product
Shift-Mode
Register Bits
These two bits identify which of the four product-shift modes (–6, 0, 1, 4) are used by PSCALE. PM resides
in ST1. See Table 6.
PREG
Product Register
32-bit register holds results of 16
×
16 multiply.
0-, 1- or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the
additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down
the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the
32-bit product shifter and from either the CALU or the Data-Write Data Bus (DWEB), and requires no cycle
overhead.
PSCALE
Product-Scaling
Shifter
TREG
Temporary
Register
16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count
for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction.
SSPCR
Synchronous
Serial-Port Control
Register
SSPCR is the control register for selecting the serial port’s mode of operation.
SDTR
Synchronous
Serial-Port
Transmit and
Receive Register
SDTR is the data-transmit and data-receive register.
TCR
Timer-Control
Register
TCR contains the control bits that define the divide-down ratio, start/stop the timer, and reload the period.
Also contained in TCR is the current count in the prescaler. Reset initializes the timer-divide-down ratio
to 0 and starts the timer.
PRD
Timer-Period
Register
PRD contains the 16-bit period that is loaded into the timer counter when the counter borrows or when the
reload bit is activated. Reset initializes the PRD to 0xFFFF.
TIM
Timer-Counter
Register
TIM contains the current 16-bit count of the timer. Reset initializes the TIM to 0xFFFF.
UART
Universal
Asynchronous
Receive/Transmit
UART is the asynchronous serial port.
ASPCR
Asynchronous
Serial-Port Control
Register
ASPCR controls the asynchronous serial-port operation.
ADTR
Asynchronous
Data Register
Asynchronous data-transmit and data-receive register
IOSR
I/O Status
Register
IOSR detects current levels (and changes with inputs) on pins IO0–IO3 and the status of UART.
BRD
Baud-Rate Divisor
Used to set the baud rate of the UART
ST0
ST1
Status Register
ST0 and ST1 contain the status of various conditions and modes. These registers can be stored in and
loaded from data memory, thereby allowing the status of the machine to be saved and restored.
IMR
Interrupt Mask
Registers
IMR individually masks or enables the seven interrupts.
IFR
Interrupt Flag
Register
IFR indicates that the CPU has latched an interrupt pulse from one of the maskable interrupts.
STACK
Stack
STACK is a block of memory used for storing return addresses for subroutines and interrupt-service
routines, or for storing data. The ’C20x stack is 16-bit wide and eight-level deep.
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