參數(shù)資料
型號： TMS320F243FN
廠商： Texas Instruments, Inc.
英文描述： 200mA, 40kHz PWM Control Circuit with 5.2V UVLO Threshold and 48% Max Duty Cycle; Package: SOIC 16 LEAD; No of Pins: 16; Container: Rail; Qty per Container: 48
中文描述： DSP控制器
文件頁數(shù)： 113/123頁
文件大?。?/td> 1205K
代理商： TMS320F243FN
www.ti.com
6.9.7.4
Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
Analog Input on
Channel Ax
Analog Input on
Channel Bx
ADC Clock
Sample and Hold
SH Pulse
t
SH
t
dschA0_n
t
dschB0_n
t
dschB0_n+1
Sample n
Sample n+1
Sample n+2
t
dschA0_n+1
t
d(SH)
ADC Event Trigger from
ePWM or Other Sources
SMODE Bit
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, or
from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected
channels on every Sample/Hold pulse. The conversion time and latency of the result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register
update. The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold
pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC
clocks wide (maximum).
NOTE
In simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and not in other combinations (such as A1/B3, etc.).
Figure 6-24. Simultaneous Sampling Mode Timing
Table 6-40. Simultaneous Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 12.5 MHz
ADC CLOCK,
t
c(ADCCLK)
= 80 nS
REMARKS
t
d(SH)
Delay time from event trigger to
sampling
Sample/Hold width/Acquisition
Width
Delay time for first result to ap-
pear in Result register
Delay time for first result to ap-
pear in Result register
Delay time for successive results
to appear in Result register
Delay time for successive results
to appear in Result register
2.5t
c(ADCCLK)
t
SH
(1 + Acqps) *
t
c(ADCCLK)
4t
c(ADCCLK)
80 ns with Acqps = 0
Acqps value = 0-15
ADCTRL1[8:11]
t
d(schA0_n)
320 ns
t
d(schB0_n)
5t
c(ADCCLK)
400 ns
t
d(schA0_n+1)
(3 + Acqps) * t
c(ADCCLK)
240 ns
t
d(schB0_n+1)
(3 + Acqps) * t
c(ADCCLK)
240 ns
Electrical Specifications
113
相關(guān)PDF資料
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