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| 型號： | TMS320F243FN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 200mA, 40kHz PWM Control Circuit with 5.2V UVLO Threshold and 48% Max Duty Cycle; Package: SOIC 16 LEAD; No of Pins: 16; Container: Rail; Qty per Container: 48 |
| 中文描述： | DSP控制器 |
| 文件頁數(shù)： | 7/123頁 |
| 文件大?。?/td> | 1205K |
| 代理商： | TMS320F243FN |
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TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
6-6
Input Clock Frequency
...........................................................................................................
89
XCLKIN Timing Requirements - PLL Enabled
................................................................................
89
XCLKIN Timing Requirements - PLL Disabled
................................................................................
89
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
.........................................................
89
Power Management and Supervisory Circuit Solutions
......................................................................
90
Reset (XRS) Timing Requirements
............................................................................................
92
General-Purpose Output Switching Characteristics
..........................................................................
93
General-Purpose Input Timing Requirements
.................................................................................
94
IDLE Mode Timing Requirements
...............................................................................................
96
IDLE Mode Switching Characteristics
..........................................................................................
96
STANDBY Mode Timing Requirements
........................................................................................
96
STANDBY Mode Switching Characteristics
..................................................................................
97
HALT Mode Timing Requirements
..............................................................................................
98
HALT Mode Switching Characteristics
........................................................................................
98
ePWM Timing Requirements
....................................................................................................
99
ePWM Switching Characteristics
................................................................................................
99
Trip-Zone input Timing Requirements
..........................................................................................
99
High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
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100
Enhanced Capture (eCAP) Timing Requirement
............................................................................
100
eCAP Switching Characteristics
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100
Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
....................................................
100
eQEP Switching Characteristics
...............................................................................................
101
External ADC Start-of-Conversion Switching Characteristics
..............................................................
101
External Interrupt Timing Requirements
......................................................................................
101
External Interrupt Switching Characteristics
.................................................................................
101
I2C Timing
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102
SPI Master Mode External Timing (Clock Phase = 0)
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103
SPI Master Mode External Timing (Clock Phase = 1)
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105
SPI Slave Mode External Timing (Clock Phase = 0)
........................................................................
106
SPI Slave Mode External Timing (Clock Phase = 1)
........................................................................
107
ADC Electrical Characteristics (over recommended operating conditions)
..............................................
109
ADC Power-Up Delays
..........................................................................................................
110
Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK)
.......................................
110
Sequential Sampling Mode Timing
............................................................................................
112
Simultaneous Sampling Mode Timing
........................................................................................
113
Flash Endurance
.................................................................................................................
115
Flash Parameters at 100-MHz SYSCLKOUT
................................................................................
115
Flash/OTP Access Timing
......................................................................................................
115
Minimum Required Wait-States at Different Frequencies
..................................................................
116
F280x Thermal Model 100-pin GGM Results
................................................................................
117
F280x Thermal Model 100-pin PZ Results
...................................................................................
117
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7-1
7-2
List of Tables
7
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