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| 型號(hào)： | TMS320LC2402 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 32A 24-32V Transient Suppressor ; Package: Can Button; No of Pins: 2; Container: Bulk; Qty per Container: 5000 |
| 中文描述： | DSP控制器 |
| 文件頁(yè)數(shù)： | 63/123頁(yè) |
| 文件大?。?/td> | 1205K |
| 代理商： | TMS320LC2402 |
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Mailbox Enable CANME
Mailbox Direction CANMD
Transmission Request Set CANTRS
Transmission Request Reset CANTRR
Transmission Acknowledge CANTA
Abort Acknowledge CANAA
Received Message Pending CANRMP
Received Message Lost CANRML
Remote Frame Pending CANRFP
Global Acceptance Mask CANGAM
Master Control CANMC
Bit-Timing Configuration CANBTC
Error and Status CANES
Transmit Error Counter CANTEC
Receive Error Counter CANREC
Global Interrupt Flag 0 CANGIF0
Global Interrupt Mask CANGIM
Global Interrupt Flag 1 CANGIF1
Mailbox Interrupt Mask CANMIM
Mailbox Interrupt Level CANMIL
Overwrite Protection Control CANOPC
TX I/O Control CANTIOC
RX I/O Control CANRIOC
Time Stamp Counter CANTSC
Time-Out Control CANTOC
Time-Out Status CANTOS
Reserved
eCAN-B Control and Status Registers
Message Identifier MSGID
Message Control MSGCTRL
Message Data Low MDL
Message Data High MDH
63E8h63E9h
63EAh63EBh
63ECh63EDh
63EEh63EFh
Message Mailbox (16 Bytes)
Control and Status Registers
6200h
623Fh
6240h
627Fh
6280h
62BFh
62C0h
62FFh
Local Acceptance Masks (LAM)
(32
×
32-Bit RAM)
eCAN-B Memory (512 Bytes)
Message Object Time Stamps (MOTS)
(32
×
32-Bit RAM)
Message Object Time-Out (MOTO)
(32
×
32-Bit RAM)
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
6300h6307h
6308h630Fh
6310h6317h
6318h631Fh
6320h6327h
eCAN-B Memory RAM (512 Bytes)
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
63E0h63E7h
63E8h63EFh
63F0h63F7h
63F8h63FFh
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
Figure 4-12. eCAN-B Memory Map
The CAN registers listed in
Table 4-7
are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Peripherals
63
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