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| 型號(hào)： | TMS320LC2402 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 32A 24-32V Transient Suppressor ; Package: Can Button; No of Pins: 2; Container: Bulk; Qty per Container: 5000 |
| 中文描述： | DSP控制器 |
| 文件頁(yè)數(shù)： | 74/123頁(yè) |
| 文件大小： | 1205K |
| 代理商： | TMS320LC2402 |
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4.11
GPIO MUX
GPxDAT (read)
Input
Qualification
GPxMUX1/2
High Impedance
Output Control
GPIOx pin
XRS
0 = Input, 1 = Output
Low Power
Modes Block
GPxDIR (latch)
Peripheral 2 Input
Peripheral 3 Input
Peripheral 1 Output
Peripheral 2 Output
Peripheral 3 Output
Peripheral 1 Output Enable
Peripheral 2 Output Enable
Peripheral 3 Output Enable
00
01
10
11
00
01
10
11
00
01
10
11
GPxCTRL
Peripheral 1 Input
N/C
GPxPUD
LPMCR0
Internal
Pullup
GPIOLMPSEL
GPxQSEL1/2
GPxSET
GPxDAT (latch)
GPxCLEAR
GPxTOGGLE
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
= Default at Reset
PIE
External Interrupt
MUX
Asynchronous
path
Asynchronous path
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO
pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin
is shown in
Figure 4-16
. Because of the open drain capabilities of the I
2
C pins, the GPIO MUX block
diagram for these pins differ. See the
TMS320x280x System Control and Interrupts Reference Guide
(literature number SPRU712) for details.
A.
x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
GPxDAT latch/read are accessed at the same memory location.
B.
Figure 4-16. GPIO MUX Block Diagram
74
Peripherals
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