參數(shù)資料
型號： TMS320LC2402PZ
廠商： Texas Instruments, Inc.
英文描述： Zero Voltage Switch Power Controller for Triacs; Package: 8 LEAD PDIP; No of Pins: 8; Container: Rail; Qty per Container: 50
中文描述： DSP控制器
文件頁數(shù)： 51/123頁
文件大小： 1205K
代理商： TMS320LC2402PZ
www.ti.com
4.4
Enhanced CAP Modules (eCAP1/2/3/4)
TSCTR
(counter32 bit)
RST
CAP1
(APRD active)
LD
CAP2
(ACMP active)
LD
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
LD
Continuous /
Oneshot
Capture Control
LD1
LD2
LD3
LD4
32
32
PRD [031]
CMP [031]
CTR [031]
eCAPx
Interrupt
Trigger
and
Flag
control
to PIE
CTR=CMP
32
32
32
32
32
ACMP
shadow
Event
Pre-scale
CTRPHS
(phase register32 bit)
SYNCOut
SYNCIn
Event
qualifier
Polarity
select
Polarity
select
Polarity
select
Polarity
select
CTR=PRD
CTR_OVF
4
PWM
compare
logic
CTR [031]
PRD [031]
CMP [031]
CTR=CMP
CTR=PRD
CTR_OVF
OVF
APWM mode
Deltamode
S
4
Capture events
CEVT[1:4]
APRD
shadow
32
32
M
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
The 280x device contains up to four enhanced capture (eCAP) modules.
Figure 4-5
shows a functional
block diagram of a module. See the
TMS320x280x Enhanced Capture (eCAP) Module Reference Guide
(literature number SPRU807) for more details.
The eCAP modules are clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP
modules
individually
(for
low
power
operation).
ECAP3ENCLK, and ECAP4ENCLK are set to low, indicating that the peripheral clock is off.
Upon
reset,
ECAP1ENCLK,
ECAP2ENCLK,
Figure 4-5. eCAP Functional Block Diagram
Peripherals
51
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相關(guān)代理商/技術(shù)參數(shù)
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