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參數(shù)資料
| 型號(hào)： | TMS320LC2402PZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Zero Voltage Switch Power Controller for Triacs; Package: 8 LEAD PDIP; No of Pins: 8; Container: Rail; Qty per Container: 50 |
| 中文描述： | DSP控制器 |
| 文件頁數(shù)： | 94/123頁 |
| 文件大?。?/td> | 1205K |
| 代理商： | TMS320LC2402PZ |
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6.8.2
GPIO - Input Timing
#!
Sampling Window
('%('
&$"
(! &
)!
(A)
GPxQSELn = 1,1 (6 samples)
Sampling Period determined
by GPxCTRL[QUALPRD]
(B)
(D)
t
w(IQSW)
t
w(SP)
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
A.
This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin
will be sampled)..
The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure 5
sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
B.
C.
D.
Figure 6-9. Sampling Mode
Table 6-13. General-Purpose Input Timing Requirements
MIN
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
QUALPRD = 0
QUALPRD
≠
0
1t
c(SCO)
t
w(SP)
Sampling period
2t
c(SCO)
* QUALPRD
t
w(SP)
* (n
(1)
- 1)
t
w(IQSW)
Input qualifier sampling window
Synchronous mode
With input qualifier
2t
c(SCO)
t
w(GPI)(2)
Pulse duration, GPIO low/high
t
w(IQSW)
+ t
w(SP)
+ 1t
c(SCO)
(1)
(2)
"n" represents the number of qualification samples as defined by GPxQSELn register.
For t
w(GPI)
, pulse width is measured from V
IL
to V
IL
for an active low signal and V
IH
to V
IH
for an active high signal.
6.8.3
Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD
≠
0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD
≠
0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
94
Electrical Specifications
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