參數(shù)資料
型號： TMS320LC2402PZ
廠商： Texas Instruments, Inc.
英文描述： Zero Voltage Switch Power Controller for Triacs; Package: 8 LEAD PDIP; No of Pins: 8; Container: Rail; Qty per Container: 50
中文描述： DSP控制器
文件頁數(shù)： 96/123頁
文件大小： 1205K
代理商： TMS320LC2402PZ
www.ti.com
WAKE INT
(A)
XCLKOUT
Addres/Data
(internal)
t
d(WAKEIDLE)
t
w(WAKEINT)
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
6.8.4
Low-Power Mode Wakeup Timing
Table 6-14
shows the timing requirements,
Table 6-15
shows the switching characteristics, and
Figure 6-11
shows the timing diagram for IDLE mode.
Table 6-14. IDLE Mode Timing Requirements
(1)
MIN
NOM
MAX
UNIT
Without input qualifier
With input qualifier
2t
c(SCO)
5t
c(SCO)
+ t
w(IQSW)
t
w(WAKE-INT)
Pulse duration, external wake-up signal
cycles
(1)
For an explanation of the input qualifier parameters, see
Table 6-13
.
Table 6-15. IDLE Mode Switching Characteristics
(1)
PARAMETER
Delay time, external wake signal to pro-
gram execution resume
(2)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20t
c(SCO)
cycles
Wake-up from Flash
–
Flash module in active state
20t
c(SCO)
+ t
w(IQSW)
1050t
c(SCO)
1050t
c(SCO)
+ t
w(IQSW)
t
d(WAKE-IDLE)
cycles
Wake-up from Flash
–
Flash module in sleep state
20t
c(SCO)
cycles
Wake-up from SARAM
20t
c(SCO)
+ t
w(IQSW)
(1)
(2)
For an explanation of the input qualifier parameters, see
Table 6-13
.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
A.
WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-11. IDLE Entry and Exit Timing
Table 6-16. STANDBY Mode Timing Requirements
TEST CONDITIONS
Without input qualification
With input qualification
(1)
MIN
NOM
MAX
UNIT
3t
c(OSCCLK)
t
w(WAKE-
INT)
Pulse duration, external
wake-up signal
cycles
(2 + QUALSTDBY) * t
c(OSCCLK)
(1)
QUALSTDBY is a 6-bit field in the LPMCR0 register.
Electrical Specifications
96
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