參數(shù)資料
型號(hào)： TMS320LC31-40
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 29/48頁
文件大小： 636K
代理商： TMS320LC31-40
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
29
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
interrupt response timing
The following table defines the timing parameters for the INT signals. The numbers shown in Figure 23
correspond with those in the NO. column of the table below.
timing parameters for INT3–INT0 response (see Figure 23)
NO.
’LC31-33
’C31-40
’LC31-40
’C31-50
’C31-60
’C31-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
50
tsu(INT-H1L)
Setup time, INT3–
INT0 before H1 low
15
13
10
8
5
ns
51
tw(INT)
Pulse duration,
interrupt to ensure
only one interrupt
P
2P
P
2P
P
2P
P
2P
P
2P
ns
This value is characterized but not tested.
P = tc(H)
The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The
TMS320C3x interrupts are evel-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1.
Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA
respond to detected interrupts on instruction-fetch boundaries only.
For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held
to:
A minimum of one H1 falling edge
No more than two H1 falling edges
The TMS320C3x can accept an interrupt from the same source every two H1 clock cycles.
If the specified timings are met, the exact sequence shown in Figure 23 occurs; otherwise, an additional delay
of one clock cycle is possible.
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