參數(shù)資料
型號： TMS320LC31-40
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processor
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 39/48頁
文件大?。?/td> 636K
代理商： TMS320LC31-40
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D
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3
HOLD timing
HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings are met, the exact sequence
shown in Figure 27 occurs; otherwise, an additional delay of one clock cycle is possible.
The table, “timing parameters for HOLD/HOLDA”, defines the timing parameters for the HOLD and HOLDA signals. The numbers shown in
Figure 27 correspond with those in the NO. column of the table.
The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set, the device comes out of hold and prevents
future hold cycles.
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a read from or a write to the
primary bus is requested. In certain circumstances, the first write is pending, thus allowing the processor to continue until a second write is
encountered.
timing parameters for HOLD/HOLDA (see Figure 27)
NO.
’LC31-33
’C31-40
’LC31-40
’C31-50
’C31-60
’C31-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
69
tsu(HOLD-H1L)
tv(H1L-HOLDA)
tw(HOLD)
tw(HOLDA)
td(H1L-SH)H
Setup time, HOLD before H1 low
15
0
13
0
10
0
8
5
ns
70
Valid time, HOLDA after H1 low
10
9
7
0
6
0
5
ns
71
Pulse duration, HOLD low
2tc(H)
tcH–5
2tc(H)
tcH–5
2tc(H)
tcH–5
2tc(H)
tcH–5
2tc(H)
tcH–5
ns
72
Pulse duration, HOLDA low
ns
73
Delay time, H1 low to STRB high for a HOLD
0§
10
0§
9
0§
7
0§
6
0§
4
ns
74
tdis(H1L-S)
Disable time, H1 low to STRB to the
high-impedance state
0§
10
0§
9
0§
8
0§
7
0§
7
ns
75
ten(H1L-S)
Enable time, H1 low to STRB enabled (active)
0§
10
0§
9
0§
7
0§
6
0§
6
ns
76
tdis(H1L-RW)
Disable time, H1 low to R/W to the
high-impedance state
0
10
0
9
0
8
0
7
0
6
ns
77
ten(H1L-RW)
Enable time, H1 low to R/W enabled (active)
0
10
0
9
0
7
0
6
0
6
ns
78
tdis(H1L-A)
Disable time, H1 low to address to the
high-impedance state
0§
10
0§
10
0§
8
0§
7
0§
7
ns
79
ten(H1L-A)
Enable time, H1 low to address enabled (valid)
0§
15
0§
13
0§
12
0§
11
0§
10
ns
80
tdis(H1H-D)
Disable time, H1 high to data to the
high-impedance state
0§
10
0§
9
0§
8
0§
7
0§
6
ns
This value is characterized but not tested
HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown in Figure 27 occurs; otherwise,
an additional delay of one clock cycle is possible.
§Not tested
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