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參數(shù)資料
| 型號(hào)： | TMS320LC545 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processors(20/25ns指令周期， 高性能，大并行度，特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的DSP) |
| 中文描述： | 數(shù)字信號(hào)處理器（20/25ns指令周期，高性能，大并行度，特殊指令集可有效實(shí)現(xiàn)多種復(fù)雜算法及應(yīng)用的數(shù)字信號(hào)處理器） |
| 文件頁數(shù)： | 22/107頁 |
| 文件大?。?/td> | 2149K |
| 代理商： | TMS320LC545 |
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TMS320C54x, TMS320LC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039A – FEBRUARY 1996 – REVISED JULY 1997
19
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
compare, select and store unit (CSSU)
The compare, select and store unit (CSSU) performs maximum comparisons between the accumulator’s high
and low word, allows the test/control (TC) flag bit of status register 0 (ST0) and the transition (TRN) register
to keep their transition histories, and selects the larger word in the accumulator to be stored in data memory.
The CSSU also accelerates Viterbi-type butterfly computation with optimized on-chip hardware.
program control
Program control is provided by several hardware and software mechanisms:
The program controller decodes instructions, manages the pipeline, stores the status of operations, and
decodes conditional operations. Some of the hardware elements included in the program controller are the
program counter, the status and control register, the stack, and the address-generation logic.
Some of the software mechanisms used for program control include branches, calls, conditional
instructions, a repeat instruction, reset, and interrupts.
power-down modes
There are three power-down modes, activated by the IDLE1, IDLE2, and IDLE3 instructions. In these modes,
the ’C54x/’LC54x devices enter a dormant state and dissipate considerably less power than in normal operation.
The IDLE1 instruction is used to shut down the CPU. The IDLE2 instruction is used to shut down the CPU and
on-chip peripherals. The IDLE3 instruction is used to shut down the ’C54x/’LC54x processor completely. This
instruction stops the PLL circuitry as well as the CPU and peripherals.
bus structure
The ’C54x/’LC54x device architecture is built around eight major 16-bit buses:
One program-read bus (PB), which carries the instruction code and immediate operands from program
memory
Two data-read buses (CB, DB) and one data-write bus (EB), which interconnect to various elements, such
as the CPU, data-address generation logic, program-address generation logic, on-chip peripherals, and
data memory
–
The CB and DB carry the operands read from data memory.
–
The EB carries the data to be written to memory.
Four address buses (PAB, CAB, DAB, and EAB), which carry the addresses needed for instruction
execution
The ’C54x/’LC54x devices have the capability to generate up to two data-memory addresses per cycle, which
are stored into two auxiliary register arithmetic units (ARAU0 and ARAU1).
The PB can carry data operands stored in program space (for instance, a coefficient table) to the multiplier for
multiply/accumulate operations or to a destination in data space for the data move instruction. This capability
allows implementation of single-cycle three-operand instructions such as FIRS.
The ’C54x/’LC54x devices also have an on-chip bidirectional bus for accessing on-chip peripherals; this bus
is connected to DB and EB through the bus exchanger in the CPU interface. Accesses using this bus can require
more than two cycles for reads and writes depending on the peripheral’s structure.
The ’C54x/’LC54x devices can have bus keepers connected to the data bus. Bus keepers ensure that the data
bus does not float. When bus keepers are enabled, the data bus maintains its previous level. Setting bit 1 of
the bank switching control register (BSCR) enables bus keepers and clearing bit 1 disables the bus keepers.
A reset automatically disables the bus keepers.
A
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