參數(shù)資料
型號: TMS320LC57S
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors(35/50ns指令周期,并行邏輯單元,可編程PLL,全雙工同步串行口的DSP)
中文描述: 數(shù)字信號處理器(35/50ns指令周期,并行邏輯單元,可編程鎖相環(huán),全雙工同步串行口的數(shù)字信號處理器)
文件頁數(shù): 18/87頁
文件大小: 1864K
代理商: TMS320LC57S
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
architecture
The ’C5x’s advanced Harvard-type architecture maximizes the processing power by maintaining two separate
memory bus structures, program and data, for full-speed execution. Instructions support data transfers between
the two spaces. This architecture permits coefficients stored in program memory to be read into the RAM,
eliminating the need for a separate coefficient ROM. The ’C5x architecture also makes available immediate
instructions and subroutines based on computed values. Increased throughput on the ’C5x for many DSP
applications is accomplished using single-cycle multiply/accumulate instructions with a data-move option, up
to eight auxiliary registers with a dedicated arithmetic unit, a parallel logic unit, and faster I/O necessary for
data-intensive signal processing. The architectural design emphasizes overall speed, communication, and
flexibility in processor configuration. Control signals and instructions provide floating-point support,
block-memory transfers, communication to slower off-chip devices, and multiprocessing implementations
as shown in the functional block diagram.
Table 3 explains the symbols that are used in the functional block diagram.
Table 3. Symbols Used in Functional Block Diagram
SYMBOL
DESCRIPTION
SYMBOL
DESCRIPTION
ABU
ACCB
ACCH
ACCL
ALU
ARAU
ARB
ARCR
ARP
ARR
AR0–AR7
AXR
BKR
BKX
BMAR
BRCR
BSP
C
CBER1
CBER2
CBSR1
CBSR2
DARAM
DBMR
DP
DRR
DXR
GREG
HPI
HPIAH
HPIAL
HPICH
Auto-buffering unit
Accumulator buffer
Accumulator high
Accumulator low
Arithmetic logic unit
Auxiliary-register arithmetic unit
Auxiliary-register pointer buffer
Auxiliary-register compare register
Auxiliary-register pointer
Address-receive register (ABU)
Auxiliary registers
Address-transmit register (ABU)
Receive-buffer-size register (ABU)
Transmit-buffer-size register (ABU)
Block-move-address register
Block-repeat-counter register
Buffered serial port
Carry bit
Circular buffer 1 end address
Circular buffer 2 end address
Circular buffer 1 start address
Circular buffer 2 start address
Dual-access RAM
Dynamic bit manipulation register
Data memory page pointer
Serial-port data receive register
Serial-port data transmit register
Global memory allocation register
Host port interface
HPI-address register (high bytes)
HPI-address register (low bytes)
HPI-control register (high bytes)
IFR
IMR
INDX
IR
MCS
MUX
PAER
PASR
PC
PFC
PLU
PMST
PRD
PREG
RPTC
SARAM
SFL
SFR
SPC
ST0,ST1
TCSR
TCR
TDM
TDXR
TIM
TRAD
TRCV
TREG0
TREG1
TREG2
TRTA
TSPC
Interrupt-flag register
Interrupt-mask register
Indirect-addressing-index register
Instruction register
Microcall stack
Multiplexer
Block-repeat-address end register
Block-repeat-address start register
Program counter
Prefetch counter
Parallel logic unit
Processor-mode-status register
Timer-period register
Product register
Repeat-counter register
Single-access RAM
Left shifter
Right shifter
Serial-port interface-control register
Status registers
TDM channel-select register
Timer-control register
Time-division-multiplexed serial port
TDM data transmit register
Timer-count register
TDM received-address register
TDM data-receive register
Temporary register for multiplication
Temporary register for dynamic shift count
Temporary register used as bit pointer in dynamic-bit test
TDM receive-/transmit-address register
TDM serial-port-control register
HPICL
HPI-control register (low bytes)
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