參數(shù)資料
型號: TMS320LC57S
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processors(35/50ns指令周期,并行邏輯單元,可編程PLL,全雙工同步串行口的DSP)
中文描述: 數(shù)字信號處理器(35/50ns指令周期,并行邏輯單元,可編程鎖相環(huán),全雙工同步串行口的數(shù)字信號處理器)
文件頁數(shù): 32/87頁
文件大?。?/td> 1864K
代理商: TMS320LC57S
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
serial ports (continued)
When auto-buffering capability is disabled (standard mode), transfers with SPI are performed under software
control through interrupts. In this mode, the ABU is transparent and the word-based interrupts (WXINT and
WRINT) provided by the SPI are sent to the CPU as transmit interrupt (XINT) and receive interrupt (RINT).
When auto buffering is enabled, word transfers are done directly between the SPI and the ’C5x internal memory,
using ABU-embedded address generators.
The ABU has its own set of circular addressing registers with corresponding address-generation units. Memory
for the buffers resides in 2K words of ’C5x internal memory. The length and starting addresses of the buffers
are user-programmable. A buffer-empty/-full interrupt can be posted to the CPU. Buffering is halted easily
because of an auto-disabling capability. Auto-buffering capability can be enabled separately for transmit and
receive sections. When auto-buffering is disabled, operation is similar to the general-purpose serial port.
The SPI allows transfer of 8-, 10-, 12-, or 16-bit data packets. In burst mode, data packets are directed by a
frame-synchronization pulse for every packet. In continuous mode, the frame-synchronization pulse occurs
when the data transmission is initiated and no further pulses occur. The frame and clock strobes are frequency
and polarity programmable. The SPI is fully static and operates at arbitrarily low clock frequencies. The
maximum operating frequency is CLKOUT1 (28.6 Mb/s at 35 ns, 40 Mb/s at 25 ns). The SPI transmit section
also includes a pulse-coded modulation (PCM) mode that allows easy interface with a PCM line.
Most ’C5x devices provide one general-purpose serial port and one TDM port. The ’C52 provides one
general-purpose serial port and no TDM port. The ’C53SX provides two general-purpose serial ports and no
TDM port. The ’LC56, ’C57S, and ’LC57 devices provide one general-purpose serial port and one buffered serial
port.
software wait-state generators
Software wait-state generation is incorporated in the ’C5x without any external hardware for interfacing with
slower off-chip memory and I/O devices. The circuitry consists of 16 wait-state generating circuits and is
user-programmable to operate with 0, 1, 2, 3, or 7 wait states. For off-chip memory accesses, these wait-state
generators are mapped on 16K-word boundaries in program memory, data memory, and the I/O ports.
The ’C53S/’C57S and ’LC56/57 devices have software-programmable wait-state generators that are controlled
by one 16-bit wait-state register PDWSR at address 0x28. The programmed number of wait states (0 through
7) applies to all external addresses at the corresponding address space (program, data, I/O) regardless of
address value.
timer
The ’C5x features a 16-bit timing circuit with a 4-bit prescaler. This timer clocks between one-half and one
thirty-second the machine rate of the device itself, depending on the programmable timer’s divide-down ratio.
This timer can be stopped, restarted, reset, or disabled by specific status bits.
The timer can be used to generate CPU interrupts periodically. The timer is decremented by one at every
CLKOUT1 cycle. A timer interrupt (TINT) and a pulse equal to the duration of a CLKOUT1 cycle on the external
TOUT pin are generated each time the counter decrements to zero. The timer provides a convenient means
of performing periodic I/O or other functions. When the timer is stopped, the internal clocks to the timer are shut
off, allowing the device to run in a low-power mode of operation.
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