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| 型號： | TMS320LC57S |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Digital Signal Processors(35/50ns指令周期，并行邏輯單元，可編程PLL，全雙工同步串行口的DSP) |
| 中文描述： | 數(shù)字信號處理器（35/50ns指令周期，并行邏輯單元，可編程鎖相環(huán)，全雙工同步串行口的數(shù)字信號處理器） |
| 文件頁數(shù)： | 34/87頁 |
| 文件大小： | 1864K |
| 代理商： | TMS320LC57S |
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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
34
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
multiprocessing (continued)
For multiprocessing applications, the ’C5x is capable of allocating global-memory space and communicating
with that space via the BR and ready control signals. Global memory is data memory shared by more than one
device. Global memory access must be arbitrated. The 8-bit memory-mapped global memory allocation register
(GREG) specifies part of the ’C5x’s data memory as global external memory. The contents of the register
determine the size of the global memory space. If the current instruction addresses an operand within that
space, BR is asserted to request control of the bus. The length of the memory cycle is controlled by the READY
line.
The ’C5x supports direct memory access (DMA) to its external program, data, and I/O spaces using the HOLD
and HOLDA signals. Another device can take complete control of the ’C5x’s external memory interface by
asserting HOLD low. This causes the ’C5x to to place its address, data, and control lines in the high-impedance
state and assert HOLDA. While external memory is being accessed, program execution from on-chip memory
can proceed concurrently when the device is in hold mode.
Multiple ’C5x devices can be interconnected through their serial ports. This form of interconnection allows
information to be transferred at high speed while using a minimum number of signal connections. A complete
full-duplex serial-port interconnection between multiple processors can be accomplished with as few as four
signal lines.
instruction set
The ’C5x microprocessor implements a comprehensive instruction set that supports both numeric-intensive
signal processing operations and general-purpose applications, such as multiprocessing and high-speed
control. Source code for the ’C1x and ’C2x DSPs is upward compatible with the ’C5x.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Because
the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an
instruction requires to execute varies, depending on whether the next data operand fetch is from internal or
external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal
or fast external program memory.
addressing modes
The ’C5x instruction set provides six basic memory-addressing modes: direct, indirect, immediate, register,
memory mapped, and circular addressing.
In direct addressing, the instruction word contains the lowest seven bits of the data-memory address. This field
is concatenated with the nine bits of the data-memory page pointer (DP) to form the 16-bit data-memory
address. Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages,
each of which contains 128 words.
Indirect addressing accesses data memory through the auxiliary registers. In indirect addressing mode, the
address of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary
registers (AR0–AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register,
the auxiliary register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
There are seven types of indirect addressing: autoincrement or autodecrement, postindexing by either adding
or subtracting the contents of AR0, single-indirect addressing with no increment or decrement, and bit-reversed
addressing (used in FFTs) with increment or decrement. All operations are performed on the current auxiliary
register in the same cycle as the original instruction, following which the current auxiliary register and ARP can
be modified.
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| TMS320LF2401AVFA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320LF2401AVFS | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320LF2402APGA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320LF2402APGAR | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 18-Bit Univ Bus Drv With 3-State Outputs RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320LF2402APGS | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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