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參數(shù)資料
| 型號(hào)： | TMS320M642AZNZ7 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1A, 52kHz (250kHz Max) Current Mode PWM Control Circuit with 16V UVLO Threshold and 48% Max Duty Cycle; Package: SOIC 14 LEAD; No of Pins: 14; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | 視頻/影像定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 72/123頁(yè) |
| 文件大小： | 1205K |
| 代理商： | TMS320M642AZNZ7 |
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4.10
Inter-Integrated Circuit (I
2
C)
TMS320F2808, TMS320F2806
TMS320F2801, UCD9501
Digital Signal Processors
SPRS230F–OCTOBER 2003–REVISED SEPTEMBER 2005
The 280x device contains one I
2
C Serial Port. Figure 4-15 shows how the I
2
C peripheral module interfaces
within the 280x device.
The I
2
C module has the following features:
Compliance with the Philips Semiconductors I
2
C-bus specification (version 2.1):
–
Support for 1-bit to 8-bit format transfers
–
7-bit and 10-bit addressing modes
–
General call
–
START byte mode
–
Support for multiple master-transmitters and slave-receivers
–
Support for multiple slave-transmitters and master-receivers
–
Combined master transmit/receive and receive/transmit mode
–
Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode rate)
One 16-bit receive FIFO and one 16-bit transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
–
Transmit-data ready
–
Receive-data ready
–
Register-access ready
–
No-acknowledgment received
–
Arbitration lost
–
Stop condition detected
–
Addressed as slave
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode
72
Peripherals
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