參數(shù)資料
型號(hào)： TMS320VC203
廠商： Texas Instruments, Inc.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進(jìn)的外圍，多種PLL可選)
中文描述： 數(shù)字信號(hào)處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進(jìn)的外圍，多種鎖相環(huán)可選）
文件頁(yè)數(shù)： 16/67頁(yè)
文件大小： 1452K
代理商： TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
input scaling shifter (continued)
The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros;
the MSBs may be either filled with zeros or sign-extended, depending upon the value of the SXM bit
(sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the
instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment
operations specific to that point in the code. The TREG base shift allows the scaling factor to be adaptable to
the system’s performance.
multiplier
The TMS320C2xx uses a 16x16-bit hardware multiplier that is capable of computing a signed or an unsigned
32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned)
instruction, perform a signed multiply operation. That is, two numbers being multiplied are treated as
2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers associated
with the multiplier:
16-bit temporary register (TREG) that holds one of the operands for the multiplier, and
32-bit product register (PREG) that holds the product.
Four product shift modes (PM) are available at the PREG’s output (PSCALE). These shift modes are useful for
performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products.
The PM field of status register ST1 specifies the PM shift mode, as shown in Table 5.
Table 5. PSCALE Product Shift Modes
PM
SHIFT
DESCRIPTION
00
no shift
Product feed to CALU or data bus with no shift.
01
left 1
Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product.
10
left 4
Removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a Q31 product
when using the multiply by a 13-bit constant.
11
right 6
Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow.
The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit
2s-complement numbers (MPY). A four-bit shift is used in conjunction with the MPY instruction with a short
immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by
a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to 128
consecutive multiply/accumulates without the possibility of overflow.
The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY
(multiply) instruction provides the section operand (also from the data bus). A multiplication can also be
performed with a 13-bit immediate operand when using the MPY instruction. A product is then obtained every
two cycles. When the code is executing multiple multiplies and product sums, the CPU supports the pipelining
of the TREG load operations with CALU operations using the previous product. These pipeline operations run
in parallel with loading the TREG include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG to
ACC and shift TREG input data (DMOV) to next address in data memory (LTD); and subtract PREG from ACC
(LTS).
Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the
multiplier, allowing both operands to be processed simultaneously. The data for these operations can be
transferred to the multiplier each cycle via the program and data buses. This facilitates single-cycle
multiply/accumulates when used with repeat (RPT) instruction. In these instructions, the coefficient addresses
are generated by program address generation (PAGEN), while the data addresses are generated by data
address generation (DAGEN). This allows the repeated instruction to sequentially access the values from the
coefficient table and step through the data in any of the indirect addressing modes.
A
相關(guān)PDF資料
PDF描述
TN-83 MICROWAVE NOISE TUBES & NOISE SOURCES
TN-101 CONNECTOR ACCESSORY
TN-102 MICROWAVE NOISE TUBES & NOISE SOURCES
TN-103 MICROWAVE NOISE TUBES & NOISE SOURCES
TN-104 CONNECTOR ACCESSORY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320VC33PGE120 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Digital Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320VC33PGE-120 制造商:Texas Instruments 功能描述:IC DSP PROCESSOR 320VC33 LQFP144 制造商:Texas Instruments 功能描述:IC, DSP PROCESSOR, 320VC33, LQFP144
TMS320VC33PGE-120 制造商:Texas Instruments 功能描述:IC DSP PROCESSOR 320VC33 LQFP144
TMS320VC33PGE120G4 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Digital Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320VC33PGE150 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Digital Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*