參數(shù)資料
型號(hào)： TMS320VC203
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Digital Signal Processors(50ns指令周期， 空閑狀態(tài)CPU全關(guān)斷，先進(jìn)的外圍，多種PLL可選)
中文描述： 數(shù)字信號(hào)處理器（50ns的指令周期，空閑狀態(tài)CPU的全關(guān)斷，先進(jìn)的外圍，多種鎖相環(huán)可選）
文件頁(yè)數(shù)： 19/67頁(yè)
文件大?。?/td> 1452K
代理商： TMS320VC203
TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 – JUNE 1995
19
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
auxiliary registers and auxiliary-register arithmetic unit (ARAU) (continued)
The auxiliary register file (AR0–AR7) is connected to the auxiliary register arithmetic unit (ARAU). The ARAU
can autoindex the current auxiliary register while the data memory location is being addressed. Indexing either
by
±
1 or by the contents of the AR0 register can be performed. As a result, accessing tables of information does
not require the CALU for address manipulation; thus, the CALU is free for other operations in parallel.
memory
The ’C2xx implements three separate address spaces for program memory, data memory, and I/O. Each space
accommodates a total of 64K 16-bit words. Within the 64K words of data space, the 256 to 32K words at the
top of the address range can be defined to be external global memory in increments of powers of two, as
specified by the contents of the global memory allocation register (GREG). Access to global memory is
arbitrated using the global memory bus request (BR) signal.
On the ’C2xx, the first 96 (0–5Fh) data memory locations are allocated for memory-mapped registers or
reserved. This memory-mapped register space contains various control and status registers including those for
the CPU.
TMS320C209 (only)
The mask-programmable ROM is located in program memory space. Customers can arrange to have this ROM
programmed with contents unique to to any particular application. The ROM is enabled or disabled by the state
of the MP/MC control input upon resetting the device. The ROM occupies the lowest block of program memory
when enabled. When disabled, these addresses are located in the device’s external program memory space.
The ’C209 devices provide two types of RAM: single-access RAM (SARAM) and dual-access RAM (DARAM).
The single-access RAM requires a full machine cycle to perform a read or a write. However, this is not one large
RAM block in which only one access per cycle is allowed. It is made up of 2K-word size-independent RAM blocks
and each one allows one CPU access per cycle. The CPU can read or write one block while accessing another
block at the same time. The ’C209 processor supports multiple accesses to its SARAM in one cycle as long as
they go to different RAM blocks. With an understanding of this structure, code and data can be appropriately
arranged to improve code performance.
The ’C2xx dual-access RAM (DARAM) allows writes to and reads from the RAM in the same cycle without the
address restrictions of the SARAM. The dual-access RAM is configured in three blocks: block 0 (B0), block 1
(B1), and block 2 (B2). Block 1 is 256 words in data memory and block 2 is 32 words in data memory. Block 0
is a 256-word block which can be configured as data or program memory. The SETC CNF (Configure B0 as
data memory) and CLRC CNF (Configure B0 as program memory) instructions allow dynamic configuration of
the memory maps through software. When using Block 0 as program memory, instructions can be downloaded
from external program memory into on-chip RAM and then executed.
TMS320C203 (only)
When using on-chip RAM, or high-speed external memory, the ’C2xx runs at full speed with no wait states. The
ability of the DARAM to allow two accesses to be performed in one cycle coupled with the parallel nature of the
’C2xx architecture enables the device to perform three concurrent memory accesses in any given machine
cycle. Externally, the READY line can be used to interface the ’C2xx to slower, less expensive external memory.
Downloading programs from slow off-chip memory to on-chip RAM can speed processing while cutting system
costs.
A
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