參數(shù)資料
型號: TMS320VC5409GGU-100
元件分類: 數(shù)字信號處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號處理器
文件頁數(shù): 18/78頁
文件大小: 1018K
代理商: TMS320VC5409GGU-100
TMS320VC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS082C – APRIL 1999 – REVISED MARCH 2000
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
parallel I/O ports
The ’5409 CPU has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the
PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The ’5409 can interface
easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
enhanced 8-bit host-port interface (HPI8/16)
The ’5409 host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard 8-bit HPI
found on earlier ’54x DSPs (’542, ’545, ’548, and ’549). The HPI8/16 is an 8-bit parallel port for interprocessor
communication. The features of the HPI8/16 include:
Standard features:
Sequential transfers (with autoincrement) or random-access transfers
Host interrupt and ’54x interrupt capability
Multiple data strobes and control pins for interface flexibility
Enhanced features of the ’5409 HPI8/16:
Access to entire on-chip RAM through DMA bus
Capability to continue transferring during emulation stop
Capability to transfer 16-bit address and 16-bit data (non-multiplexed mode)
The HPI8/16 functions as a slave and enables the host processor to access the on-chip memory of the ’5409.
A major enhancement to the ’5409 HPI over previous versions is that it allows host access to the entire on-chip
memory range of the DSP. The HPI8/16 does not have access to external memory. The host and the DSP both
have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock. If
the host and the DSP contend for access to the same location, the host has priority, and the DSP waits for one
HPI8/16 cycle. Note that since host accesses are always synchronized to the ’5409 clock, an active input clock
(CLKIN) is required for HPI8/16 accesses during IDLE states, and host accesses are not allowed while the ’5409
reset pin is asserted.
0000h
005Fh
Reserved
0060h
007Fh
0080h
Scratch-Pad
RAM
7FFFh
8000h
On-Chip RAM
(32K x 16 Bits)
FFFFh
Reserved
Figure 6. ’5409 HPI Memory Map
standard 8-bit mode
The HPI8/16 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit
transfers are accomplished in two parts with the HBIL input designating high or low byte. The host
communicates with the HPI8 through three dedicated registers — HPI address register (HPIA), HPI data
register (HPID), and an HPI control register (HPIC). The HPIA and HPID registers are only accessible by the
host, and the HPIC register is accessible by both the host and the ’5409. If the HPI is disabled (HPIENA = 0)
or in HPI16 mode (HPI16 = 1), the 8-bit bidirectional data pins HD0–HD7 can be used as general-purpose
input/output (GPIO).
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