參數(shù)資料
型號： TMS320VC5409GGU-100
元件分類： 數(shù)字信號處理
英文描述： 16-Bit Digital Signal Processor
中文描述： 16位數(shù)字信號處理器
文件頁數(shù)： 6/78頁
文件大?。?/td> 1018K
代理商： TMS320VC5409GGU-100
TMS320VC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS082C – APRIL 1999 – REVISED MARCH 2000
6
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
terminal functions
The ’5409 signal descriptions table lists each pin name, function, and operating mode(s) for the ’5409 device.
Some of the ’5409 pins can be configured for one of two functions; a primary function and a secondary function.
The names of these pins in secondary mode are shaded in grey in the following table.
Terminal Functions
TERMINAL
NAME
INTERNAL
PIN STATE
I/O
DESCRIPTION
DATA SIGNALS
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(MSB)
(LSB)
Bus holders
available
(A15–A0)
O/Z
Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The
lower sixteen address pins (A15 to A0) are multiplexed to address all external memory (program,
data) or I/O while the upper seven address pins (A22 to A16) are only used to address external
program space. These pins are placed in the high-impedance state when the hold mode is enabled,
or when OFF is low.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
(LSB)
Bus holders
available
I/O/Z
Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D15 to D0) are multiplexed
to transfer data between the core CPU and external data/program memory or I/O devices. The data
bus is placed in the high-impedance state when not outputting or when RS or HOLD is asserted.
The data bus also goes into the high-impedance state when OFF is low.
The data bus has bus holders to reduce the static power dissipation caused by floating, unused
pins. These bus holders also eliminate the need for external bias resistors on unused pins. When
the data bus is not being driven by the ’5409, the bus holders keep the pins at the previous logic
level. The data bus holders on the ’5409 are disabled at reset and can be enabled/disabled via the
BH bit of the bank-switching control register (BSCR).
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
IACK
O/Z
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter
is fetching the interrupt vector location designated by A15–A0. IACK also goes into the
high-impedance state when OFF is low.
INT0
INT1
INT2
INT3
I = Input, O = Output, Z = High-impedance, S = Supply
Schmitt
trigger
I
External user interrupts. INT0–INT3 are prioritized and are maskable by the interrupt mask register
and the interrupt mode bit. INT0 –INT3 can be polled and reset by way of the interrupt flag register.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320VC5409GGU-80 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320VC5409PGE100 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Sig Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320VC5409PGE100 制造商:Texas Instruments 功能描述:Digital Signal Processor IC
TMS320VC5409PGE-80 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320VC5409ZGU100 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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