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參數(shù)資料
| 型號： | TMS32C6205DGHKA200 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 32/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIXED POINT DSP 288-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TMS320C62x |
| 類型： | 定點 |
| 接口： | McBSP，PCI |
| 時鐘速率： | 200MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 128kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.50V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 288-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 288-BGA Microstar（16x16） |
| 包裝： | 托盤 |
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TMS320C6205
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS106G OCTOBER 1999 REVISED JULY 2006
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles§ (see Figure 15 Figure 18)
NO.
200
UNIT
NO.
MIN
MAX
UNIT
3
tsu(EDV-AREH)
Setup time, EDx valid before ARE high
1.5
ns
4
th(AREH-EDV)
Hold time, EDx valid after ARE high
3.5
ns
6
tsu(ARDYH-AREL)
Setup time, ARDY high before ARE low
[(RST 3) * P 6]
ns
7
th(AREL-ARDYH)
Hold time, ARDY high after ARE low
(RST 3) * P + 3
ns
9
tsu(ARDYL-AREL)
Setup time, ARDY low before ARE low
[(RST 3) * P 6]
ns
10
th(AREL-ARDYL)
Hold time, ARDY low after ARE low
(RST 3) * P + 3
ns
11
tw(ARDYH)
Pulse width, ARDY high
2P
ns
15
tsu(ARDYH-AWEL) Setup time, ARDY high before AWE low
[(WST 3) * P 6]
ns
16
th(AWEL-ARDYH)
Hold time, ARDY high after AWE low
(WST 3) * P + 3
ns
18
tsu(ARDYL-AWEL)
Setup time, ARDY low before AWE low
[(WST 3) * P 6]
ns
19
th(AWEL-ARDYL)
Hold time, ARDY low after AWE low
(WST 3) * P + 3
ns
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
switching characteristics over recommended operating conditions for asynchronous memory
cycles§# (see Figure 15 Figure 18)
NO.
PARAMETER
200
UNIT
NO.
PARAMETER
MIN
TYP
MAX
UNIT
1
tosu(SELV-AREL)
Output setup time, select signals valid to ARE low
RS * P 2
ns
2
toh(AREH-SELIV)
Output hold time, ARE high to select signals invalid
RH * P 2
ns
5
tw(AREL)
Pulse width, ARE low
RST * P
ns
8
td(ARDYH-AREH)
Delay time, ARDY high to ARE high
3P
4P + 5
ns
12
tosu(SELV-AWEL)
Output setup time, select signals valid to AWE low
WS * P 2
ns
13
toh(AWEH-SELIV)
Output hold time, AWE high to select signals invalid
WH * P 2
ns
14
tw(AWEL)
Pulse width, AWE low
WST * P
ns
17
td(ARDYH-AWEH)
Delay time, ARDY high to AWE high
3P
4P + 5
ns
RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
§ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
# Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional
7P ns following the end of the cycle.
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