參數(shù)資料
型號: TMX320DM648ZUT900
廠商: Texas Instruments, Inc.
英文描述: Digital Media Processor
中文描述: 數(shù)字媒體處理器
文件頁數(shù): 109/166頁
文件大小: 1341K
代理商: TMX320DM648ZUT900
www.ti.com
P
VPxCLKINx
2
3
1
4
4
TMS320DM647/TMS320DM648
Digital Media Processor
SPRS372–MAY 2007
6.11.3.3
VCLKIN Timing (Video Display Mode)
Table 6-38. Timing Requirements for Video Display Mode for VPxCLKINx
(1)
(see
Figure 6-23
)
-720
-900
NO.
UNIT
MIN
MAX
1
2
3
4
t
c(VKI)
t
w(VKIH)
t
w(VKIL)
t
t(VKI)
The reference points for the rise and fall transitions are measured at V
IL
MAX and V
IH
MIN.
Cycle time, VPxCLKINx
Pulse duration, VPxCLKINx high
Pulse duration, VPxCLKINx low
Transition time, VPxCLKINx
9
ns
ns
ns
ns
4.1
4.1
3
(1)
Figure 6-23. Video Port Display VPxCLKINx Timing
6.11.3.4
Video Control Input/Output and Video Display Data Output Timing With Respect to VPxCLKINx
and VPxCLKOUTx (Video Display Mode)
Table 6-39. Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to
VPxCLKINx and VPxCLKOUTx (see
Figure 6-24
)
-720
-900
NO.
UNIT
MIN
2.9
0.5
7.4
–0.9
MAX
13
14
15
16
t
su(VCTLV-VKIH)
t
h(VCTLV-VKIH)
t
su(VCTLV-VKOH)
t
h(VCTLV-VKOH)
Assuming non-inverted VPxCLKOUTx signal.
Setup time, VPxCTLx valid before VPxCLKINx high
Hold time, VPxCTLx valid after VPxCLKINx high
Setup time, VPxCTLx valid before VPxCLKOUTx high
(1)
Hold time, VPxCTLx valid after VPxCLKOUTx high
(1)
ns
ns
ns
ns
(1)
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Peripheral Information and Electrical Specifications
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