參數(shù)資料
型號(hào)： TMX320F2810PGFS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁數(shù)： 43/103頁
文件大小： 1341K
代理商： TMX320F2810PGFS
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
external interrupts (continued)
The masked interrupts, XINT1/2 and NMI, also contain a 16-bit up-counter register that is reset to 0x0000
whenever an interrupt edge is detected. This counter can be used to accurately time stamp the occurrence of
the interrupt. Table 30 shows the bit definitions of the XINT1/2CTR and XNMICTR registers.
Table 30. XINT1/2CTR and XNMICTR Registers Bit Definitions
BITS
NAME
TYPE
RESET
DESCRIPTION
15:0
INTCTR
R
0:0
This is a free running 16-bit up-counter that is clocked at the SYSCLKOUT rate. The
counter value is reset to 0x0000 when a valid interrupt edge is detected and then continues
counting until the next valid interrupt edge is detected. The counter must only be reset by
the selected POLARITY edge as selected in the respective interrupt control register. When
the interrupt is disabled, the counter will stop. The counter is a free-running counter and
will wrap around to zero when the max value is reached. The counter is a read only register
and can only be reset to zero by a valid interrupt edge or by reset.
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