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參數(shù)資料
| 型號： | TMX320F2810PGFS |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 60/103頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | TMX320F2810PGFS |
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
60
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
32-bit CPU-Timers 0/1/2 (continued)
Table 49. TIMERxTPR Register Bit Definitions
BITS
NAME
R/W
RESET
DESCRIPTION
7:0
TDDR
R/W
0x00
Timer Divide-Down. Every (TDDRH:TDDR + 1) timer clock source cycles, the timer counter
register (TIMH:TIM) decrements by one. At reset, the TDDRH:TDDR bits are cleared to 0. To
increase the overall timer count by an integer factor, write this factor minus one to the
TDDRH:TDDR bits. When the prescaler counter (PSCH:PSC) value is 0, one timer clock source
cycle later, the contents of the TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM
decrements by one. TDDRH:TDDR also reloads the PSCH:PSC whenever the timer reload bit
(TRB) is set by software.
15:8
PSC
R
0x00
Timer Prescale Counter. These bits hold the current prescale count for the timer. For every timer
clock source cycle that the PSCH:PSC value is greater than 0, the PSCH:PSC decrements by one.
One timer clock (output of the timer prescaler) cycle after the PSCH:PSC reaches 0, the
PSCH:PSC is loaded with the contents of the TDDRH:TDDR, and the timer counter register
(TIMH:TIM) decrements by one. The PSCH:PSC is also reloaded whenever the timer reload bit
(TRB) is set by software. The PSCH:PSC can be checked by reading the register, but it cannot be
set directly. It must get its value from the timer divide-down register (TDDRH:TDDR). At reset, the
PSCH:PSC is set to 0.
x = 0, 1, or 2
Table 50. TIMERxTPRH Register Bit Definitions
BIT
NAME
R/W
RESET
DESCRIPTION
7:0
TDDRH
R/W
0x00
See description of TIMERxTPR.
15:8
PSCH
R
0x00
See description of TIMERxTPR.
x = 0, 1, or 2
P
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