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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | TP3057WM/NOPB |
| 寤犲晢锛� | National Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 14/18闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC INTERFACE ENHANCED SER 16SOIC |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 45 |
| 椤炲瀷锛� | PCM 绶ㄨВ纰煎櫒/婵炬尝鍣� |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| ADC / DAC 鏁�(sh霉)閲忥細 | 1 / 2 |
| 涓夎绌嶅垎瑾�(di脿o)璁婏細 | 鐒� |
| 闆诲 - 闆绘簮锛屾ā鎿細 | ±5V |
| 闆诲 - 闆绘簮锛屾暩(sh霉)瀛楋細 | ±5V |
| 宸ヤ綔婧害锛� | -25°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 16-SOIC锛�0.295"锛�7.50mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 16-SOIC W |
| 鍖呰锛� | 绠′欢 |
| 鍏跺畠鍚嶇ū锛� | *TP3057WM *TP3057WM/NOPB TP3057WM TP3057WM-ND |
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Functional Description (Continued)
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors
see
Figure 4 The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real-
ized The op amp drives a unity-gain filter consisting of RC
active pre-filter followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz The output of
this filter directly drives the encoder sample-and-hold circuit
The AD is of companding type according to m-law
(TP3054) or A-law (TP3057) coding conventions A preci-
sion voltage reference is trimmed in manufacturing to pro-
vide an input overload (tMAX) of nominally 25V peak (see
table of Transmission Characteristics) The FSX frame sync
pulse controls the sampling of the filter output and then the
successive-approximation encoding cycle begins The 8-bit
code is then loaded into a buffer and shifted out through DX
at the next FSX pulse The total encoding delay will be ap-
proximately 165 ms (due to the transmit filter) plus 125 ms
(due to encoding delay) which totals 290 ms Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz The decoder is A-law (TP3057) or
m
-law (TP3054) and the 5th order low pass filter corrects for
the sin xx attenuation due to the 8 kHz samplehold The
filter is then followed by a 2nd order RC active post-filter
power amplifer capable of driving a 600X load to a level of
72 dBm The receive section is unity-gain Upon the occur-
rence of FSR the data at the DR input is clocked in on the
falling edge of the next eight BCLKR (BCLKX) periods At
the end of the decoder time slot the decoding cycle begins
and 10 ms later the decoder DAC output is updated The
total decoder delay is E 10 ms (decoder update) plus
110 ms (filter delay) plus 625 ms(
frame) which gives
approximately 180 ms
4
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| TP3057V/NOPB | IC INTERFACE ENHANCED SER 20PLCC |
| TP3067N/NOPB | IC INTERFACE ENHANCED SER 20-DIP |
| TP3067WM/NOPB | IC INTERFACE ENHANCED SER 20SOIC |
| TP3054WM-X/NOPB | IC INTERFACE ENHANCED SER 16SOIC |
| VI-26B-CU | CONVERTER MOD DC/DC 95V 200W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| TP3057WMX | 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel |
| TP3057WMX/NOPB | 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel |
| TP3057-X | 鍒堕€犲晢:NSC 鍒堕€犲晢鍏ㄧū:National Semiconductor 鍔熻兘鎻忚堪:Extended Temperature Serial Interface CODEC/Filter COMBO Family |
| TP3058 | 鍒堕€犲晢:NSC 鍒堕€犲晢鍏ㄧū:National Semiconductor 鍔熻兘鎻忚堪:MICROPROCESSOR COMPATIBLE COMBO-R |
| TP3058J | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:u-Law CODEC |
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