Timing Specifications Unless otherwise noted limits printed in BOLD characters are guaranteed for V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� TP3057WM/NOPB
寤犲晢锛� National Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 16/18闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC INTERFACE ENHANCED SER 16SOIC
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 45
椤炲瀷锛� PCM 绶ㄨВ纰煎櫒/婵炬尝鍣�
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闆诲 - 闆绘簮锛屾ā鎿細 ±5V
闆诲 - 闆绘簮锛屾暩(sh霉)瀛楋細 ±5V
宸ヤ綔婧害锛� -25°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 16-SOIC锛�0.295"锛�7.50mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 16-SOIC W
鍖呰锛� 绠′欢
鍏跺畠鍚嶇ū锛� *TP3057WM
*TP3057WM/NOPB
TP3057WM
TP3057WM-ND
Timing Specifications Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC e
50V g5% VBB eb50V g5% TA e 0 Cto70 C by correlation with 100% electrical testing at TA e 25 C All other limits are
assured by correlation with other production tests andor product design and characterization All signals referenced to GNDA
Typicals specified at VCC e 50V VBB eb50V TA e 25 C All timing parameters are measured at VOH e 20V and VOL e
07V See Definitions and Timing Conventions section for test methods information
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1tPM
Frequency of Master Clocks
Depends on the Device Used and the
1536
MHz
BCLKR CLKSEL Pin
1544
MHz
MCLKX and MCLKR
2048
MHz
tRM
Rise Time of Master Clock
MCLKX and MCLKR
50
ns
tFM
Fall Time of Master Clock
MCLKX and MCLKR
50
ns
tPB
Period of Bit Clock
485
488
15725
ns
tRB
Rise Time of Bit Clock
BCLKX and BCLKR
50
ns
tFB
Fall Time of Bit Clock
BCLKX and BCLKR
50
ns
tWMH
Width of Master Clock High
MCLKX and MCLKR
160
ns
tWML
Width of Master Clock Low
MCLKX and MCLKR
160
ns
tSBFM
Set-Up Time from BCLKX High
First Bit Clock after the Leading
100
ns
to MCLKX Falling Edge
Edge of FSX
tSFFM
Set-Up Time from FSX High
Long Frame Only
100
ns
to MCLKX Falling Edge
tWBH
Width of Bit Clock High
VIHe22V
160
ns
tWBL
Width of Bit Clock Low
VILe06V
160
ns
tHBFL
Holding Time from Bit Clock
Long Frame Only
0
ns
Low to Frame Sync
tHBFS
Holding Time from Bit Clock
Short Frame Only
0
ns
High to Frame Sync
tSFB
Set-Up Time from Frame Sync
Long Frame Only
80
ns
to Bit Clock Low
tDBD
Delay Time from BCLKX High
Loade150 pF plus 2 LSTTL Loads
0
140
ns
to Data Valid
tDBTS
Delay Time to TSX Low
Loade150 pF plus 2 LSTTL Loads
140
ns
tDZC
Delay Time from BCLKX Low to
CLe0 pF to 150 pF
50
165
ns
Data Output Disabled
tDZF
Delay Time to Valid Data from
CLe0 pF to 150 pF
20
165
ns
FSX or BCLKX Whichever
Comes Later
tSDB
Set-Up Time from DR Valid to
50
ns
BCLKRX Low
tHBD
Hold Time from BCLKRX Low to
50
ns
DR Invalid
tSF
Set-Up Time from FSXR to
Short Frame Sync Pulse (1 Bit Clock
50
ns
BCLKXRLow
Period Long)
tHF
Hold Time from BCLKXR Low
Short Frame Sync Pulse (1 Bit Clock
100
ns
to FSXR Low
Period Long)
tHBFl
Hold Time from 3rd Period of
Long Frame Sync Pulse (from 3 to 8 Bit
100
ns
Bit Clock Low to Frame Sync
Clock Periods Long)
(FSX or FSR)
tWFL
Minimum Width of the Frame
64k Bits Operating Mode
160
ns
Sync Pulse (Low Level)
6
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
TP3057V/NOPB IC INTERFACE ENHANCED SER 20PLCC
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TP3067WM/NOPB IC INTERFACE ENHANCED SER 20SOIC
TP3054WM-X/NOPB IC INTERFACE ENHANCED SER 16SOIC
VI-26B-CU CONVERTER MOD DC/DC 95V 200W
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鍙冩暩(sh霉)鎻忚堪
TP3057WMX 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
TP3057WMX/NOPB 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel
TP3057-X 鍒堕€犲晢:NSC 鍒堕€犲晢鍏ㄧū:National Semiconductor 鍔熻兘鎻忚堪:Extended Temperature Serial Interface CODEC/Filter COMBO Family
TP3058 鍒堕€犲晢:NSC 鍒堕€犲晢鍏ㄧū:National Semiconductor 鍔熻兘鎻忚堪:MICROPROCESSOR COMPATIBLE COMBO-R
TP3058J 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:u-Law CODEC
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