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參數資料
型號: TPA6140A2YFFR
廠商: Texas Instruments
文件頁數: 26/30頁
文件大?。?/td> 0K
描述: IC AMP AUDIO 25MW STER 16DSBGA
視頻文件: TPA6140A2 Demonstration
標準包裝: 1
系列: DirectPath™
類型: G 類
輸出類型: 耳機,2-通道(立體聲)
在某負載時最大輸出功率 x 通道數量: 32mW x 2 @ 32 歐姆
電源電壓: 2.5 V ~ 5.5 V
特點: 消除爆音,差分輸入,I²C,靜音,短路和熱保護,關機,音量控制
安裝類型: 表面貼裝
供應商設備封裝: 16-DSBGA(1.56x1.56)
封裝/外殼: 16-UFBGA,DSBGA
包裝: 標準包裝
產品目錄頁面: 878 (CN2011-ZH PDF)
配用: 296-24299-ND - EVALUATION MODULE FOR TPA6140A2
其它名稱: 296-24237-6
SCL
SDA
tw(H)
tw(L)
tsu1
th1
www.ti.com................................................................................................................................................. SLOS598A – MARCH 2009 – REVISED OCTOBER 2009
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PSRR
Power supply rejection ratio
AVDD = 2.5 V to 5.5 V, inputs grounded, GAIN = 0 dB
90
105
dB
CMRR
Common-mode rejection ratio
HPVDD = 1.3 V to 1.8 V, GAIN = 0 dB
68
dB
|IIH|
High-level input current
AVDD = 2.5 V to 5.5 V, VI = AVDD
SCL, SDA
1
A
|IIL|
Low-level input current
AVDD = 2.5 V to 5.5 V, VI = 0 V
SCL, SDA
1
A
ISD
Soft shutdown current
SW Shutdown mode, VDD = 2.5 V to 5.5 V, SWS bit = 1
1
3
A
AVDD = 3.6 V HPVDD = 1.3 V, Amplifiers active, no load, no
1.2
2.0
input signal
AVDD = 3.6 V, POUT = 100 μW into 32
(1), f
AUD = 1 kHz
2.5
IDD
Total supply current
AVDD = 3.6 V, POUT = 500 μW into 32
(1), f
AUD = 1 kHz
4.0
mA
AVDD = 3.6 V, POUT = 1 mW into 32
(1), f
AUD = 1 kHz
6.8
AVDD = 3.6 V, HiZ_L = HiZ_R = HIGH (High output impedance
1.0
2.0
mode)
(1)
Per channel output power assuming a 10 dB crest factor
TIMING CHARACTERISTICS
For I
2C interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCL
Frequency, SCL
No wait states
400
kHz
tW(H)
Pulse duration, SCL high
0.6
μs
tW(L)
Pulse duration, SCL low
1.3
μs
tSU1
Setup time, SDA to SCL
100
μs
tH1
Hold time, SCL to SDA
10
ns
t(BUF)
Bus free time between stop and start condition
1.3
μs
tSU2
Setup time, SCL to start condition
0.6
μs
tH2
Hold time, start condition to SCL
0.6
μs
tSU3
Setup time, SCL to stop condition
0.6
μs
Figure 1. SCL and SDA Timing
Copyright 2009, Texas Instruments Incorporated
5
Product Folder Link(s): TPA6140A2
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