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參數(shù)資料
| 型號： | TPS54310PWPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 6 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | GREEN, PLASTIC, HTSSOP-20 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 463K |
| 代理商： | TPS54310PWPRG4 |
www.ti.com
PIN ASSIGNMENTS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AGND
VSENSE
COMP
PWRGD
BOOT
PH
RT
SYNC
SS/ENA
VBIAS
VIN
PGND
PWP PACKAGE
(TOP VIEW)
SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor
AGND
1
and SYNC pin. Make PowerPAD connection to AGND.
Bootstrap input. 0.022-F to 0.1-F low-ESR capacitor connected from BOOT to PH generates floating drive for
BOOT
5
the high-side FET driver.
COMP
3
Error amplifier output. Connect compensation network from COMP to VSENSE.
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
PGND
11–13
areas to the input and output supply returns, and negative terminals of the input and output capacitors.
PH
6–10
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
Power good open drain output. High when VSENSE
≥ 90% V
ref, otherwise PWRGD is low. Note that output is low
PWRGD
4
when SS/ENA is low or internal shutdown signal active.
RT
20
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
SS/ENA
18
capacitor input to externally set the start-up time.
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin
SYNC
19
select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor
must be connected to the RT pin.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with
VBIAS
17
a high quality, low ESR 0.1-F to 1.0-F ceramic capacitor.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
VIN
14–16
device package with a high quality, low ESR 1-F to 10-F ceramic capacitor.
VSENSE
2
Error amplifier inverting input.
5
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