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參數(shù)資料
| 型號： | TPS54310PWPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 6 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | GREEN, PLASTIC, HTSSOP-20 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 463K |
| 代理商： | TPS54310PWPRG4 |
www.ti.com
Error Amplifier
PWM Control
Dead-Time Control and MOSFET Drivers
Overcurrent Protection
SLVS412D – DECEMBER 2001 – REVISED FEBRUARY 2007
Table 1. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥ 2.5 V
Float
Externally set 280 kHz to 700 kHz
Float
R = 68 k to 180 k
Externally synchronized frequency
Synchronization signal
R = RT value for 80% of external synchronization frequency
The high performance, wide bandwidth, voltage error
low-side FET remains on until the VSENSE voltage
amplifier sets the TPS54310 apart from most dc/dc
decreases
to
a
range
that
allows
the
PWM
converters. The user is given the flexibility to use a
comparator to change states. The TPS54310 is
wide range of output L and C filter components to
capable of sinking current continuously until the
suit the particular needs of the application. Type 2 or
output reaches the regulation set-point.
type
3
compensation
can
be
employed
using
If the current limit comparator trips for longer than
external compensation components.
100 ns, the PWM latch resets before the PWM ramp
exceeds the error amplifier output. The high-side
FET turns off and low-side FET turns on to decrease
Signals from the error amplifier output, oscillator, and
the energy in the output inductor and consequently
current limit circuit are processed by the PWM
the output current. This process is repeated each
control logic. Referring to the internal block diagram,
cycle in which the current limit comparator is tripped.
the control logic includes the PWM comparator, OR
gate, PWM latch, and portions of the adaptive
dead-time
and
control
logic
block.
During
Adaptive dead-time control prevents shoot-through
steady-state
operation
below
the
current
limit
current from flowing in both N-channel power
threshold, the PWM comparator output and oscillator
MOSFETs during the switching transitions by actively
pulse train alternately reset and set the PWM latch.
controlling the turn-on times of the MOSFET drivers.
Once the PWM latch is set, the low-side FET
The high-side driver does not turn on until the gate
remains on for a minimum duration set by the
drive voltage to the low-side FET is below 2 V. The
oscillator pulse duration. During this period, the PWM
low-side driver does not turn on until the voltage at
ramp discharges rapidly to its valley voltage. When
the gate of the high-side MOSFETs is below 2 V.
the ramp begins to charge back up, the low-side FET
The high-side and low-side drivers are designed with
turns off and high-side FET turns on. As the PWM
300-mA source and sink capability to quickly drive
ramp voltage exceeds the error amplifier output
the power MOSFETs gates. The low-side driver is
voltage, the PWM comparator resets the latch, thus
supplied from VIN, while the high-side drive is
turning off the high-side FET and turning on the
supplied from the BOOT pin. A bootstrap circuit uses
low-side FET. The low-side FET remains on until the
an external BOOT capacitor and an internal 2.5-
next oscillator pulse discharges the PWM ramp.
bootstrap switch connected between the VIN and
During transient conditions, the error amplifier output
BOOT
pins.
The
integrated
bootstrap
switch
could be below the PWM ramp valley voltage or
improves drive efficiency and reduces external
above the PWM peak voltage. If the error amplifier is
component count.
high, the PWM latch is never reset and the high-side
FET remains on until the oscillator pulse signals the
control logic to turn the high-side FET off and the
The cycle by cycle current limiting is achieved by
low-side FET on. The device operates at
its
sensing the current flowing through the high-side
maximum duty cycle until the output voltage rises to
MOSFET and differential amplifier and comparing it
the
regulation
set-point,
setting
VSENSE
to
to the preset overcurrent threshold. The high-side
approximately the same voltage as Vref. If the error
MOSFET is turned off within 200 ns of reaching the
amplifier output is low, the PWM latch is continually
current limit threshold. A 100-ns leading edge
reset and the high-side FET does not turn on. The
blanking circuit prevents false tripping of the current
limit. Current limit detection occurs only when current
flows from VIN to PH when sourcing current to the
output filter. Load protection during current sink
operation is provided by thermal shutdown.
13
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TPS54310-Q1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTERRATED FERs (SWIFT) |
| TPS54310QPWPRQ1 | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 3V-6Vin 3A Output Synch-Buck PWM Sw RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS54311 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs |
| TPS54311-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTa?￠) |
| TPS54311MPWPREP | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 Mil Enh 3V-6V 3A Out Synch-Buck PWM Sw RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
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