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參數(shù)資料
| 型號： | TPS54610QPWPRG4Q1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 12 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | GREEN, PLASTIC, HTSSOP-28 |
| 文件頁數(shù)： | 19/22頁 |
| 文件大?。?/td> | 527K |
| 代理商： | TPS54610QPWPRG4Q1 |
www.ti.com
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AGND
VSENSE
COMP
PWRGD
BOOT
PH
RT
SYNC
SS/ENA
VBIAS
VIN
PGND
PWP PACKAGE
(TOP VIEW)
THERMAL
PAD
SLVS726 – JANUARY 2007
Terminal Functions
TERMINAL
DESCRIPTION
NAME
NO.
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT
resistor and SYNC pin. Connect PowerPAD to AGND.
BOOT
5
Bootstrap output. 0.022-F to 0.1-F low-ESR capacitor connected from BOOT to PH generates floating drive for
the high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
PGND
15-19
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single
point connection to AGND is recommended.
PH
6-14
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High when VSENSE
≥ 90% V
ref, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or the internal shutdown signal is active.
RT
28
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using
the SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.
SS/ENA
26
Slow-start/enable input/output. Dual function pin that provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
SYNC
27
Synchronization input. Dual function pin that provides logic input to synchronize to an external oscillator or pin
select between two internally set switching frequencies. When used to synchronize to an external signal, a
resistor must be connected to the RT pin.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with
a high quality, low-ESR 0.1-F to 1.0-F ceramic capacitor.
VIN
20-24
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low-ESR 10-F ceramic capacitor.
VSENSE
2
Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
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