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參數(shù)資料
| 型號： | TPS54610QPWPRG4Q1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 12 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | GREEN, PLASTIC, HTSSOP-28 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 527K |
| 代理商： | TPS54610QPWPRG4Q1 |
www.ti.com
DETAILED DESCRIPTION
UNDERVOLTAGE LOCK OUT (UVLO)
VBIAS REGULATOR (VBIAS)
SLOW-START/ENABLE (SS/ENA)
VOLTAGE REFERENCE
OSCILLATOR AND PWM RAMP
t
d +
C
(SS)
1.2 V
5 mA
(2)
Switching Frequency +
100 kW
R
500 [kHz]
(4)
t
(SS) +
C
(SS)
0.7 V
5 mA
(3)
SLVS726 – JANUARY 2007
The
TPS54610
incorporates
an
under
voltage
The VBIAS regulator provides internal analog and
lockout circuit to keep the device disabled when the
digital blocks with a stable supply voltage over
input voltage (VIN) is insufficient. During power up,
variations in junction temperature and input voltage.
internal circuits are held inactive until VIN exceeds
A high quality, low-ESR, ceramic bypass capacitor is
the nominal UVLO threshold voltage of 2.95 V. Once
required on the VBIAS pin. X7R or X5R grade
the UVLO start threshold is reached, device start-up
dielectrics are recommended because their values
begins. The device operates until VIN falls below the
are more stable over temperature. The bypass
nominal UVLO stop threshold of 2.8 V. Hysteresis in
capacitor must be placed close to the VBIAS pin and
the UVLO comparator, and a 2.5-s rising and falling
returned to AGND.
edge deglitch circuit reduce the likelihood of shutting
External loading on VBIAS is allowed, with the
the device down due to noise on VIN.
caution that internal circuits require a minimum
VBIAS of 2.70 V, and external loads on VBIAS with
ac
or
digital
switching
noise
may
degrade
performance. The VBIAS pin may be useful as a
The slow-start/enable pin provides two functions.
reference voltage for external circuits.
First, the pin acts as an enable (shutdown) control by
keeping the device turned off until the voltage
exceeds the start threshold voltage of approximately
1.2 V. When SS/ENA exceeds the enable threshold,
The voltage reference system produces a precise
device start-up begins. The reference voltage fed to
Vref signal by scaling the output of a temperature
the error amplifier is linearly ramped up from 0 V to
stable bandgap circuit. During manufacture, the
0.891 V in 3.35 ms. Similarly, the converter output
bandgap and scaling circuits are trimmed to produce
voltage reaches regulation in approximately 3.35 ms.
0.891 V at the output of the error amplifier, with the
Voltage hysteresis and a 2.5-s falling edge deglitch
amplifier connected as a voltage follower. The trim
circuit reduce the likelihood of triggering the enable
procedure adds to the high precision regulation of
due to noise.
the TPS54610, because it cancels offset errors in the
The second function of the SS/ENA pin provides an
scale and error amplifier circuits.
external means of extending the slow-start time with
a low-value capacitor connected between SS/ENA
and AGND.
The oscillator frequency can be set to internally fixed
Adding a capacitor to the SS/ENA pin has two
values of 350 kHz or 550 kHz using the SYNC pin as
effects on start-up. First, a delay occurs between
a static digital input. If a different frequency of
release of the SS/ENA pin and start-up of the output.
operation is required for the application, the oscillator
The delay is proportional to the slow-start capacitor
frequency can be externally adjusted from 280 to
value and lasts until the SS/ENA pin reaches the
700 kHz by connecting a resistor between the RT pin
enable
threshold.
The
start-up
delay
is
and AGND and floating the SYNC pin. The switching
approximately:
frequency is approximated by the following equation,
where R is the resistance from RT to AGND:
Second, as the output becomes active, a brief
External synchronization of the PWM ramp is
ramp-up at the internal slow-start rate may be
possible over the frequency range of 330 kHz to 700
observed before the externally set slow-start rate
kHz by driving a synchronization signal into SYNC
takes control and the output rises at a rate
and connecting a resistor from RT to AGND. Choose
proportional
to
the
slow-start
capacitor.
The
a resistor between the RT and AGND, which sets the
slow-start time set by the capacitor is approximately:
free running frequency to 80% of the synchronization
signal. The following table summarizes the frequency
selection configurations:
The actual slow-start time is likely to be less than the
above approximation due to the brief ramp-up at the
internal rate.
15
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參數(shù)描述 |
|---|---|
| TPS54610QPWPRQ1 | 制造商:Texas Instruments 功能描述:CONV DC-DC SGL-OUT STEP DOWN 28HTSSOP - Tape and Reel |
| TPS54611 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs |
| TPS54611-EP | 制造商:TI 制造商全稱:Texas Instruments 功能描述:3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTa?￠) |
| TPS54611PWP | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 Lo-In Voltage 6A Sync Buck Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| TPS54611PWPG4 | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 Lo-In Voltage 6A Sync Buck Converter RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
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