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參數(shù)資料
| 型號(hào)： | TQ1089 |
| 廠商： | TriQuint Semiconductor,Inc. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 193K |
| 代理商： | TQ1089 |
TQ1089
2
For additional information and latest specifications, see our website:
www.triquint.com
In the test mode, the PLL is bypassed and REFCLK is
connected directly to the Divide Logic block via the
MUX, as shown in Figure 1. This mode is useful for
debug and test purposes. The test mode is outlined
in Table 2.
The maximum rise and fall time at the output pins is 1.4
ns. All outputs of the TQ1089 are TTL-compatible with 30
mA symmetric drive and a minimum V
OH
of 2.4 V.
Power Up/Reset Synchronization
After power up or reset, the PLL requires time before it
achieves synchronization lock. The maximum time
required for synchronization (TSYNC) is 500 ms.
Table 1. Frequency Mode Selection
Functional Description
The core of the TQ1089 is a Phase-Locked Loop (PLL)
that continuously compares the reference clock
(REFCLK) to the feedback clock (FBIN), maintaining a
zero frequency difference between the two. Since one
of the outputs is always connected to FBIN, the PLL
keeps the propagation delay between the outputs and
the reference clock within –350 ps +500 ps for the
TQ1089–MC500, and within –350 ps +700 ps for the
TQ1089–MC700.
The internal Voltage-Controlled Oscillator (VCO), has an
operating range of 260 MHz to 360 MHz, as shown in
Table 1. The combination of the VCO and the Divide
Logic enables the TQ1089 to operate between 65 MHz
and 90 MHz and from 130 MHz to 180 MHz.
Table 2. Test Mode Selection
Group A
Outputs Q0–Q8
Group B
Outputs Q9, Q10
Test
Mode
Ref. Clock
1
÷
2
f
REF
f
REF
÷
4
f
REF
÷
2
Output
Feedback
Reference Clock
Frequency Range
Output Frequency Range
Group A: Q0–Q8
Test
Mode
Group B: Q9,Q10
0
0
Group B
Group A
÷
2
÷
4
130 MHz – 180 MHz
65 MHz – 90 MHz
65 MHz – 90 MHz
65 MHz – 90 MHz
130 MHz – 180 MHz
130 MHz – 180 MHz
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