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參數(shù)資料
| 型號(hào)： | TQ1089 |
| 廠商： | TriQuint Semiconductor,Inc. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 193K |
| 代理商： | TQ1089 |
TQ1089
3
S
P
For additional information and latest specifications, see our website:
www.triquint.com
Layout Guidelines
Multiple ground and power pins on the TQ1089 reduce
ground bounce. Good layout techniques, however, are
necessary to guarantee proper operation and to meet
the specifications across the full operating range.
TriQuint recommends bypassing each of the V
DD
supply
pins to the nearest ground pin, as close to the chip
as possible.
Figure 2 shows the recommended power layout for the
TQ1089. The bypass capacitors should be located on
the same side of the board as the TQ1089. The V
DD
traces connect to an inner-layer V
DD
plane. All of the
ground pins (GND) are connected to a small ground
plane on the surface beneath the chip. Multiple through
holes connect this small surface plane to an inner-layer
ground plane. The capacitors (C1–C5) are 0.1 mF.
TriQuint’s test board uses X7R temperature-stable
capacitors in 1206 SMD cases.
C4
C5
C1
C2
C3
Pin 1
Pin 15
Ground
Plane
V
DD
V
DD
V
DD
V
DD
V
DD
Figure 2. Top Layer Layout of Power Pins
(Approx. 3.3x)
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