TQ5135
Data Sheet
14
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A small amount of inductance is needed frompin 16 to
ground for proper degeneration of the LNA input
stage. Too much inductance at this point will degrade
LNA gain, while too little inductance will degrade NF at
the conjugate match. Because of stray inductance on
the application board layout, it is difficult to give a
precise value in nH. Thus we recommend during the
prototype stage to use one of the copper patterns in
Figure 13.
A short can be placed across the pattern and its
position varied until the desired gain is met. Then the
unused copper can be removed for the final product.
2. Determine the LNA Matching Network
Matching network design for the TQ5135 LNA is much
simpler than designing with discrete transistors. The
TQ5135 LNA was designed so that the optimumnoise
match is very close to the conjugate match. Thus
once a match to 50ohms is attained, only a slight
adjustment to the L and C values may be needed for
optimumnoise figure. If the design uses 5-8ml
dielectric FR4 board, then it is likely that the
component values on the evaluation board can be
used for a starting point. Alternately, a network can
be synthesized fromthe S-parameter values at the
end of this note.
3. LO Buffer Tuning
The drain of the LO buffer is brought out to pin 10
where it is fed DC bias via an inductor. The inductor
resonates with the internal and external parasitic
capacitance associated with that pin. For maximum
performance the resonance must be at or near the
desired LO frequency. Figure 14 shows a properly
tuned LO buffer. Notice that the LO frequency range
of interest is to the left of the peak. We recommend
that the LO is tuned slightly higher in frequency, so
that the desired band is on the lower, more gradual
side of the slope. Thus there is less change in
performance versus frequency. We have also found
empirically that tuning the LO slightly higher in
frequency results in much better LO input and RF
input matches.
TQ5135
G
GND
RF In
GND
LNA
Bias
MXR
In
I
I
GND
LO
In
G
L
V
DD
N
V
D
L
TQ5135
G
GND
RF In
GND
LNA
Bias
MXR
In
I
I
GND
LO
In
G
L
V
DD
N
V
D
L
Figure 13: LNA Source Inductor Realization