參數(shù)資料
型號(hào): TQ6122
廠商: TriQuint Semiconductor,Inc.
英文描述: 1 Gigasample/sec, 8-bit Digital-to-Analog Converter
中文描述: 1 Gigasample /秒,8位數(shù)字到模擬轉(zhuǎn)換器
文件頁數(shù): 15/23頁
文件大?。?/td> 939K
代理商: TQ6122
TQ6122
15
For additional information and latest specifications, see our website:
www.triquint.com
M
P
Clock Input
In order to realize the full speed potential of the DAC, a
clock with an input swing of at least 1 V peak-to-peak,
nominally centered on –1.3 V, is required. The clock
may be applied in either single-ended or differential
fashion. Because a differential clock provides maximum
speed and best control of the relationship between clock
and output transitions, as well as minimum noise,
it is
the preferred solution. For single-ended clock drive, the
customer must drive the unused CLOCK input with an
external ECL reference level, which may be generated
using a resistive divider or, for best results, an external
inverter tied back on itself. See Figure 15.
Input Line Termination
As shown in Figure 14, data, control, and clock inputs
should be terminated in 50 ohms to V
TT
, consistent
with good ECL practice. For best results, keep
terminations physically small — surface-mount “chip”
resistors work very well — and locate them as close to
the IC as possible. The V
TT
bus should also be locally
bypassed to digital ground, using chip capacitors
placed close to the terminations. The DAC offers good
performance for –2.5 V < V
TT
< –2 V, where the use of
V
TT
< –2 V may allow the designer to eke out the last
bit of performance in a noisy or marginal drive-level
environment.
Current-Source Control Loop
As illustrated previously in Figure 13, and shown in
detail in Figure 16, the bit current sources are
controlled by placing them in a feedback loop which
compares the drop across a current-sensing resistor
with a stable reference. For nominal 1 Volt full-scale
output swing, the V
REF
-to-V
AA
voltage will be in the 0.8
to 1 V range, and may be derived from a zener or,
better still, a bandgap reference such as the 2.5 V
Motorola MC1403A. The output of the bandgap
reference will have to be divided down before being
applied to the control op amp, and some means should
be provided to trim the output to compensate for V
OUT
load resistor variations.
The op amp must have input common-mode and
output drive ranges which extend down to within at
least 0.5 Volt of the negative rail for maximum control
range. For best noise immunity, both the reference
generator and the op amp should share a point
connection to the V
AA
rail, close to the DAC. The
Motorola MC33071 op amp is suitable for this
application. Standard linear design techniques should
be used to minimize thermal drift and offset. Note that
the temperature coefficient of the nichrome resistors
used in the DAC is on the order of +6 ppm/
°
C. Figure 16
shows a typical reference control loop circuit.
IREF
VAA
VREF
VSENSE
BLK.DIS.
AGND
VOUT
VOUT
AGND
AGND
DGND
+
MC1403A
V PLANE
V
V (V + 2.5 V)
MC33071
1uF
0.01
1000
2.5 K
2.5 K
V
V
620
(V +1 V)
V
+
1 K
V
AA
CC
EE
AA
AA
1 K
(I = ON)
(I = OFF)
VAA
V
V
OUT
OUT
Fig. 16. Typical External Current-Source Control Loop
Figure 17 illustrates the relationship between control
input V
REF
and the full-scale output swing. Note that the
full-scale swing may be reduced below 0.25 V peak-to-
peak by pulling V
REF
below V
AA
. However, this
necessitates a separate negative supply for the control
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