參數(shù)資料
型號: TQ6122
廠商: TriQuint Semiconductor,Inc.
英文描述: 1 Gigasample/sec, 8-bit Digital-to-Analog Converter
中文描述: 1 Gigasample /秒,8位數(shù)字到模擬轉(zhuǎn)換器
文件頁數(shù): 8/23頁
文件大小: 939K
代理商: TQ6122
TQ6122
8
For additional information and latest specifications, see our website:
www.triquint.com
Mechanical Characteristics
The TQ6122 DAC is packaged in a proprietary 44-pin
multilayer ceramic package which provides high-speed,
controlled-impedance interconnects and integral power
supply bypassing. The leads are set on 0.050” centers,
and are formed for gull-wing surface mounting. Figure
8 shows the pinout diagram of the packaged IC as seen
from the top, opposite the cavity side; Figure 9 lists pin
numbers, names and I/O levels. Figure 10 illustrates
the pertinent dimensions of the package and Figure 11
shows the mounting footprint.
Since the TQ6122 dissipates on the order of 1.3 W,
adequate heat sinking is essential for proper operation
of the device. Figure 12 shows one possible heat sink
arrangement based on a multi-finned “Top Hat” heat
sink available from Thermalloy. An environment with a
minimum of 100 fpm (feet per minute) of forced air
cooling is assumed; >200 fpm is preferred.
Figure 8. TQ6122 Pinout
23
12
11
34
PIN 1
VAA
IREF
ECL REF
A0
A1
DGND
A2
A3
A4
A5
VSS
VSS
CLOCK
CLOCK
N/C
SELA
DGND
BLANK
B7
B6
B5
VSS
TQ6122AM
TOP VIEW
OF MLC-44 PACKAGE
AS IT SITS ON
CIRCUIT BOARD
(CAVITY IS DOWN)
V
V
V
B
A
V
V
A
A
A
V
V
A
A
D
B
B
D
B
B
B
V
Notes: 1. A7, B7 = MSB inputs
2. N/C = no internal connection
Pin
Signal
Interface Level (Typ.)
1
, 11, 12,
33, 34, 44
2
3
4
5
6, 28,
37, 40
7
8
9
10
13–15, 18
16
17
19
V
SS
–5 V
B5
B6
B7 (
MSB
)
BLANK
D
GND
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
0 V
SELA
CLOCK
CLOCK
A
GND
V
OUT
V
OUT
BLANK
DISABLE
V
SENSE
600 mV pk–pk centered at –1.3 V @ DC
No connection
1V pk–pk centered at –1.3 V @ AC
1V pk–pk centered at –1.3 V @ AC
0 V
0 V to –1 V
–1 V to 0 V
Enable = V
AA
(I
BLANK
= ON)
Disable = A
GND
(I
BLANK
= OFF)
V
AA
+ 0.8, for V
FS
= 1 V pk–pk
20
Figure 9. TQ6122 Pin Descriptions
Pin
Signal
Interface Level (Typ.)
21
22, 23
24
25
26
27
29
30
31
32
35
36
38
39
41
42
43
V
REF
V
AA
I
REF
ECL REF
A0 (
LSB
)
A1
A2
A3
A4
A5
A6
A7 (
MSB
)
B0 (
LSB
)
B1
B2
B3
B4
V
AA
+1, for V
FS
= 1V pk–pk
–5 V
2.5 mA for V
FS
= 1V pk–pk
–1.3 V
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
600 mV pk–pk centered at –1.3 V @ DC
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