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TQ8101C
T
P
5
For additional information and latest specifications, see our website:
www.triquint.com
Control
The signals on pins CNTL(3:0) can be used to control
the clock rate, clock mode, loopback scheme, and
tristate pins. Also, the internal PLL high-speed clock
may be disabled, allowing an external clock source to
be used on the MXHCN and MXHCP pins.
Note that the NAND tree enable normally is used only
for device testing of the V
IH
and V
IL
parameters.
Table 1. Modes of Operation
CNTL(3:0)
Modes of operation
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
Reset
Tristate all TTL outputs except DXRCK and MO
NAND-tree test all TTL inputs except CNTL(3:0)
DXRCK tristate
Frame recovery disable
Equipment loopback
Facility loopback
Split loopback
Bypass, slave, internal VCO disabled, STS-3 rate
Bypass, master, internal VCO disabled, STS-3 rate
Bypass, slave, internal VCO disabled, STS-12 rate
Bypass, master, internal VCO disabled, STS-12 rate
Normal, slave, internal VCO enabled, STS-3 rate
Normal, master, internal VCO enabled, STS-3 rate
Normal, slave, internal VCO enabled, STS-12 rate
Normal, master, internal VCO enabled, STS-12 rate
Notes: “Bypass” indicates the use of the external high-speed clock in lieu of the internal transmit PLL.
“Normal” indicates use of the internal transmit PLL.
“Master” derives PLL timing from the reference 51.84-MHz oscillator input, MXLRC
“Slave” derives PLL timing from the demultiplexer clock input, RXCK.
At power-up or during initialization, CNTL(3) should
be set to logic 1. During reset, all internal counters,
dividers, and loopback states, and the phase-
frequency detector, are reset or deactivated. Note that
frame search is initiated only by a rising edge on OOF.