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參數(shù)資料
| 型號： | TS(X)PC603EVAB/C4LL |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 120 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | CERAMIC, QFP-240 |
| 文件頁數(shù)： | 37/38頁 |
| 文件大?。?/td> | 632K |
| 代理商： | TS(X)PC603EVAB/C4LL |
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TSPC603E
8/38
3. SIGNAL DESCRIPTION
Figure 4, Table 3 and Table 4 describe the signal on the TSPC603e and indicate signal functions. The test signals, TRST, TMS, TCK,
TDI and TDO, comply with subset P-1149.1 of the IEEE testability bus standard.
The 3 signals LSSD_MODE, LI_TSTCLK and L2_TSTCLK are test signals for factory use only and must be pulled up to VDD for
normal machine operations.
BR
BG
ABB
TS
TT[0-4]
AP[0-3]
APE
TBST
TSIZ[0-2]
GBL
CI
WT
CSE[0-1]
TC[0-1]
AACK
ARTRY
SYSCLK
CLK_OUT
PLL_CFG[0-3]
DBG
DBWO
DBB
DPE
DP[0-7]
DH[0-31], DL[0-31]
A[0-31]
DBDIS
TA
DRTRY
TEA
INT, SMI
MCP
HRESET, SRESET
CKSTP_IN, CKSTP_OUT
RSRV
QREQ, QACK
TBEN
TLBISYNC
TRST, TCK, TMS, TDI, TD0
5
LSSD_MODE,
L1_TSTCLK, L2_TSTCLK
3
1
VDD
OVDD
GND*
OGND*
AVDD
ADDRESS
ARBITRATION
ADDRESS
START
ADDRESS
BUS
TRANSFER
ATTRIBUTE
ADDRESS
TERMINATION
CLOCKS
DATA
ATTRIBUTION
DATA
TRANSFER
DATA
TERMINATION
INTERRUPTS
CHECKSTOPS
RESET
PROCESSOR
STATUS
JTAG/COP
INTERFACE
LSSD TEST
CONTROL
POWER SUPPLY
64
8
1
2
1
2
1
2
1
(20) 13
(19) 23
15
23
1
32
4
1
5
3
1
2
4
1
2
1
603e
(*) Ground inputs not separated on CBGA package
(number) Pin number in CBGA package
(40)
{
Figure 4 : Functional signal groups
Table 3 : Address and data bus signal index
Signal name
Mnemonic
Signal function
Signal
type
Address bus
A[0-31]
if output, physical address of data to be transferred.
if input, represents the physical address of a snoop operation.
I/O
Data bus
DH[0-31]
Represents the state of data, during a data write operation if output, or
during a data read operation if input.
I/O
Data bus
DL[0-31]
Represents the state of data, during a data write operation if output, or
during a data read operation if input.
I/O
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