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參數(shù)資料
| 型號(hào)： | TS(X)PC603EVAB/C4LL |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 120 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | CERAMIC, QFP-240 |
| 文件頁數(shù)： | 9/38頁 |
| 文件大小： | 632K |
| 代理商： | TS(X)PC603EVAB/C4LL |
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TSPC603E
17/38
3.7. Marking
The document where are defined the marking are identified in the related reference documents. Each microcircuit are legible and
permanently marked with the following information as minimum :
- Thomson logo,
- Manufacturer’s part number,
- Class B identification if applicable,
- Date-code of inspection lot,
- ESD identifier if available,
- Country of manufacturing.
4. ELECTRICAL CHARACTERISTICS
4.1. General requirements
All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given
below :
- Table 9 : Static electrical characteristics for the electrical variants.
- Table 10 : Dynamic electrical characteristics for the 603e.
These specifications are for 80 MHz and 100 MHz processor core frequencies. The processor core frequency is determined by the
bus (SYSCLK) frequency and the settings of the PLL_CFG0_PLL_CFG3 signals. All timings are specified respective to the rise edge
of SYSCLK.
4.2. Static characteristics
Table 9 : Electrical characteristics
Vdd = 3.3
± 5 % V dc, GND = 0 V dc, –55°C ≤ Tc ≤ 125°C
Characteristics
Symbol
Min
Max
Unit
Input high voltage (all inputs except SYSCLK)
VIH
2.0
5.5
V
Input low voltage (all inputs except SYSCLK)
VIL
GND
0.8
V
SYSCLK input high voltage
CVIH
2.4
5.5
V
SYSCLK input low voltage
CVIL
GND
0.4
V
Input leakage current
Vin = 3.465 V(1)
Iin
-
10
mA
Vin = 5.5 V1
Iin
-
245
mA
Hi-Z (off-state)
Vin = 3.465 V(1)
leakage current
ITSI
-
10
mA
Vin = 5.5 V(1)
ITSI
-
245
mA
Output high voltage
IOH = –9 mA
VOH
2.4
-
V
Output low voltage
IOL = 14 mA
VOL
-
0.4
V
Capacitance, Vin = 0 V, f = 1 MHz(2)
(excludes TS, ABB, DBB, and ARTRY)
Cin
-
10.0
pF
Capacitance, Vin = 0 V, f = 1 MHz(2)
(for TS, ABB, DBB, and ARTRY)
Cin
-
15.0
pF
Notes : 1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals).
2. Capacitance is periodically sampled rather than 100 % tested.
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