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參數(shù)資料
| 型號： | TS(X)PC603EVAB/C4LL |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 120 MHz, RISC PROCESSOR, CQFP240 |
| 封裝： | CERAMIC, QFP-240 |
| 文件頁數(shù)： | 6/38頁 |
| 文件大?。?/td> | 632K |
| 代理商： | TS(X)PC603EVAB/C4LL |
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TSPC603E
14/38
Table 6 : Thermal resistance and junction temperature
Configuration
qja (°C/W)
Tj (°C)
Exposed die (no heat sink)
18.4
86
With 2338 heat sink
5.3
53
Vendors such as Aavid Engineering Inc., Thermalloy, and Wakefield Engineering can supply heat sinks with a wide range of thermal
performance.
3.6. Power consideration
The PowerPC603e microprocessor is the first microprocessor specifically designed for low-power operation. The 603e provides both
automatic and program-controllable power reduction modes for progressive reduction of power consumption. This chapter describes
the hardware support provided by the 603e for power management.
3.6.1. Dynamic Power Management
Dynamic power management automatically powers up and down the individual execution units of the 603e, based upon the contents
of the instruction stream. For example, if no floating-point instructions are being executed, the floating-point unit is automatically pow-
ered down. Power is not actually removed from the execution unit ; instead, each execution unit has an independent clock input,
which is automatically controlled on a clock-by- clock basis. Since CMOS circuits consume negligible power when they are not
switching, stopping the clock to an execution unit effectively eliminates its power consumption. The operation of DPM is completely
transparent to software or any external hardware. Dynamic power management is enabled by setting bit 11 in HID0 on power-up, of
following HRESET.
3.6.2. Programmable Power Modes
The 603e provides four programmable power states - full power, doze, nap and sleep. Software selects these modes by setting one
(and only one) of the three power saving mode bits. Hardware can enable a power management state through external asynchronous
interrupts The hardware interrupt causes the transfer of program flow to interrupt handler code. The appropriate mode is then set by
the software. The 603e provides a separate interrupt and interrupt vector for power management - the system management interrupt
(SMI). The 603e also contains a decrement timer which allows it to enter the nap or doze mode for a predetermined amount of time
and then return to full power operation through the decrementer interrupt (DI). Note that the 603e cannot switch from on power man-
agement mode to another without first returning to full on mode. The nap and sleep modes disable bus snooping ; therefore, a hard-
ware handshake is provided to ensure coherency before the 603e enters these power management modes. Table 7 summarizes the
four power states.
Table 7 : Power PC 603e Microprocessor Programmable Power Modes
PM Mode
Functioning Units
Activation Method
Full-Power Wake Up Method
Full power
All units active
–
Full power (with DPM)
Requested logic by
demand
By instruction dispatch
–
Doze
- Bus snooping
- Data cache as needed
- Decrementer timer
Controlled by SW
External asynchronous exceptions*
Decrementer interrupt
Reset
Nap
Decrementer timer
Controlled by hardware and
software
External asynchronous exceptions
Decrementer interrupt
Reset
Sleep
None
Controlled by hardware and
software
External asynchronous exceptions
Reset
* Exceptions are referred to as interrupts in the architecture specification
3.6.3. Power Management Modes
The following sections describe the characteristics of the 603e’s power management modes, the requirements for entering and exit-
ing the various modes, and the system capabilities provided by the 603e while the power management modes are active.
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