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參數(shù)資料
| 型號： | TS68230CFN10 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時(shí)器 |
| 文件頁數(shù)： | 14/61頁 |
| 文件大小： | 2911K |
| 代理商： | TS68230CFN10 |
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5. H2(H4) may be an output pin in the pulsed in-
put handshake protocol. It is asserted exactly
as in the interlocked input protocol, but never
remains asserted longer than four clock cy-
cles. Typically, a four clock cycle pulse is ge-
nerated. But in the case that a subsequent
H1(H3) asserted edge occurs before termina-
tion of the pulse, H2(H4) is negated asynchro-
nously. Thus, anytime after the leading edge of
the H2(H4) pulse, new data may be entered in
the PI/T double-buffered input latches. The
H2S(H4S) status bit is always zero. When H12
enable (H34 enable) is zero, H2(H4) is held ne-
gated.
2.1.3. DOUBLE-BUFFERED OUTPUT TRANS-
FERS. The PI/T supports double-buffered output
transfers in all modes. Data, written by the bus mas-
ter to the PI/T, is stored in the port’s output latch. The
peripheral accepts the data by asserting H1(H3),
which causes the next data to be moved to the port’s
output latch as soon as it is available. The function
of H2(H4) is programmable ; it may indicate whether
data has been moved to the output latch or it may
serve other purposes. The H1S(H3S) status bit may
be programmed for two interpretations. First, the
status bit is a one when there is at least one latch in
the double-buffered data path that can accept new
data. After writing one byte/word of data to the ports,
an interrupt service routine could check this bit to de-
termine if it could store another byte/word, thus filling
both latches. Second, when the bus master is finis-
hed, it is often useful to be able to check whether all
of the data has been transferred to the peripheral.
The H1S(H3S) status bit is set when both output
latches are empty. The programmable options of the
H2(H4) pin are given below, depending on the
mode.
1. H2(H4) may be an edge-sensitive input pin in-
dependent of H1(H3) and the transfer of port
data. On the asserted edge of H2(H4), the
H2S(H4S) status bit is set. It is cleared by the
direct method (refer to
2.3 Direct Method of
Resetting Status
), the RESET pin being as-
serted, or when the H12 enable (H34 enable)
bit of the port general control register is zero.
2. H2(H4) may be a general-purpose output pin
that is always zero.
3. H2(H4) may be a general-purpose output pin
that is always asserted. The H2S(H4s) status
bit is always zero.
4. H2(H4) may be an output pin in the interlocked
output handshake protocol. H2(H4) is asser-
ted two clock cycles after data is transferred to
the double-buffered output latches. The data
remains stable and H2(H4) remains asserted
until the next asserted edge of the H1(H3) in-
put. At that time, H2(H4) is asynchronously ne-
gated. As soon as the next data is available, it
is transferred to the output latches and H2(H4)
is asserted. When H2(H4) is negated, asser-
ted transitions on H1(H3) have no effect on the
data paths. As is explained later, however, in
modes 2 and 3 H1 does control the three-state
output buffers of the bidirectional port(s). The
H2S(H4S) status bit is always zero. When H12
enable (H34 enable) is zero, H2(H4) is held ne-
gated.
Figure 2.1 :
Double-Buffered Input Transfers Timing Diagram.
TS68230
14/61
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PDF描述 |
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| TS68230FN | HMOS PARALLEL INTERFACE/TIMER |
| TS68230 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230CP10 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230CP8 | HMOS PARALLEL INTERFACE/TIMER |
| TS68230P | HMOS PARALLEL INTERFACE/TIMER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TS68230CFN8 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
| TS68230CP10 | 制造商:STME 功能描述: |
| TS68230CP8 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
| TS68230FN | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:HMOS PARALLEL INTERFACE/TIMER |
| TS68230MC1B/C10 | 制造商:e2v technologies 功能描述: |
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