參數(shù)資料
型號(hào): TS68230CFN10
廠(chǎng)商: 意法半導(dǎo)體
英文描述: HMOS PARALLEL INTERFACE/TIMER
中文描述: HMO的并行接口/定時(shí)器
文件頁(yè)數(shù): 35/61頁(yè)
文件大?。?/td> 2911K
代理商: TS68230CFN10
Programmable Options Mode 3 - Port A Submode XX and Port B Submode XX
PACR
7 6
X X
PACR
5 4 3
X X 0
X X 1
PACR
2
0
1
PACR
1
0
1
PACR
0
0
It is clear when both latches are full and cannot accept new data.
1
The H1S status bit is set when both of the port B output latches are empty. It is clear when at
least one latch is full.
PBCR
7 6
Port B Submode
X X
Submode XX.
PBCR
5 4 3
H4 Control
X X 0
Output pin - interlocked input handshake protocol, H4S is always clear.
X X 1
Output pin - pulsed input handshake, H4S is always clear.
PBCR
2
H4 Interrupt Enable
0
The H4 interrupt is disabled.
1
The H4 interrupt is enabled.
PBCR
1
H3 SVCRQ Enable
0
The H3 interrupt and DMA request are disabled.
1
The H3 interrupt and DMA request are enabled.
PBCR
0
H3 Status Control
X
The H3S status bit is set anytime input data is present in the double-buffered input path.
Port A Submode
Submode XX.
H2 Control
Output pin - interlocked output handshake protocol, H2S status always cleared.
Output pin - pulsed output handshake protocol, H2S status always cleared.
H2 Interrupt Enable
The H2 interrupt is disabled.
The H2 interrupt is enabled.
H1 SVCRQ Enable
The H1 interrupt and DMA request are disabled.
The H1 interrupt and DMA request are enabled.
H1 Status Control
The H1 status bit is set when either the port B initial or final output latch can accept new data.
TS68230
35/61
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