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參數(shù)資料
| 型號： | TS68302 |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Multiprotocol Processor IMP |
| 中文描述： | 集成多協(xié)議處理器進(jìn)出口 |
| 文件頁數(shù)： | 31/47頁 |
| 文件大?。?/td> | 1149K |
| 代理商： | TS68302 |
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31
TS68302
2117A–HIREL–11/02
Figure 24.
GSI Timing Diagram
Notes:
1. The ratio CLK/TCLK1 must be greater than 2.5/1.
2. L1T x D becomes valid after the L1CLK rising edge or the sync enable, whichever is later, if long frames are used.
3. Specification valid for both sync methods.
4. See Figure 25.
Table 21.
AC Electrical Specifications - PCM Timing
(4)
f = 16.67 MHz
There are two sync types:
Short frame - Sync signals are one clock cycle prior to the data.
Long frame - Sync signals are N-bits that envelope the data, N > 0.
Num.
Parameter
Min
Max
Unit
300
L1CLK (PCM clock) frequency
(1)
6.66
MHz
301
L1CLK width low/high
55
ns
302
L1SY0-L1SY1 setup time to L1CLK falling edge
20
ns
303
L1SY0-L1SY1 hold time from L1CLK falling edge
40
ns
304
L1SY0-L1SY1 width low
1
L1CLK
305
Time between successive sync signals (short frame)
8
L1CLK
306
L1T x D data valid after L1CLK rising edge
(2)
0
70
ns
307
L1T x D to high impedance (from L1CLK rising edge)
0
50
ns
308
L1R x D setup time (to L1CLK falling edge)
(3)
20
ns
309
L1R x D hold time (from L1CLK falling edge)
(3)
50
ns
310
L1T x D data valid after syncs rising edge (long)
(2)
0
100
ns
311
L1T x D to high impedance (from L1SY0-L1SY1 falling edge) (long)
0
70
ns
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| TS68302CA1B/C16 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Multiprotocol Processor IMP |
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| TS68302DESC01QXC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Integrated Multiprotocol Processor IMP |
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