參數(shù)資料
型號(hào)： TS68302
廠商： Atmel Corp.
英文描述： Integrated Multiprotocol Processor IMP
中文描述： 集成多協(xié)議處理器進(jìn)出口
文件頁(yè)數(shù)： 40/47頁(yè)
文件大小： 1149K
代理商： TS68302
40
TS68302
2117A–HIREL–11/02
detection of frames that are too long,
programmable 0 - 15 FLAGS between successive frames,
automatic retransmission in case of collision.
The SCC BISYNC mode key features are as follows:
flexible data buffers,
eight control recognition registers,
automatic SYNC1 and SYNC2 detection,
SYNC/DLE stripping and insertion,
CRC-16 and LRC generation/checking,
parity (VRC) generation/checking,
supports BISYNC transparent operation (use of DLE characters),
supports promiscuous (totally transparent) reception and transmission,
maintains parity error counter,
external SYNC support,
reverse data mode.
The SCC DDCMP mode key features are as follows:
synchronous and asynchronous DDCMP links supported,
flexible data buffers,
four address comparison registers with mask,
automatic frame synchronization,
automatic message synchronization by searching for SOH, ENQ, or DLE,
CRC-16 generation/checking,
NRZ/NRZI data encoding,
maintenance of four 16-bit error counters.
The SCC V.110 mode key features are as follows:
provides synchronization and reception of 80-bit frames,
automatic detection of framing errors,
allows transmission of the 80-bit frame.
The SCC UART mode key features are as follows:
flexible message-oriented data buffers,
multidrop operation,
receiver wakeup on idle line or address mode,
eight control character comparison registers,
two address comparison registers,
four 16-bit error counters,
programmable data length (7 - 8 bits),
programmable 1 or 2 stop bits with fractional stop bits,
even/odd/force/no parity generation,
even/odd/no parity check,
frame error, noise error, break, and idle detection,
transmits idle and break sequences,
freeze transmission option,
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