參數(shù)資料
型號： TS68302DESC01QYA
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： Integrated Multiprotocol Processor IMP
中文描述： 16-BIT, 16.67 MHz, RISC MICROCONTROLLER, CQFP132
封裝： CERAMIC, QFP-132
文件頁數(shù)： 37/47頁
文件大?。?/td> 1149K
代理商： TS68302DESC01QYA
37
TS68302
2117A–HIREL–11/02
Dual-Port RAM
The IMP has 1152 bytes of RAM configured as a dual-port memory. The RAM can be
accessed by the internal RISC controller or one of three bus masters: the 68000 core,
an external bus master, or the IDMA. All internal bus masters synchronously access the
RAM with no wait states. External bus masters can access the RAM and registers syn-
chronously or asynchronously.
The RAM is divided into two parts. There are 576 bytes used as a parameter RAM,
which includes pointers, counters, and registers for the serial ports. The other 576 bytes
may be used for system RAM, which may include data buffers, or may be used for other
purposes such as a no-wait-state cache.
Timers
There are three timer units. Two units are identical, general-purpose timers; the third
unit can be used to implement a watchdog timer function.
The two general-purpose timers are implemented with a timer mode register (TMR), a
timer capture register (TCR), a timer counter (TCN), a timer reference register (TRR),
and a timer event register (TER). The TMR contains the prescaler value programmed by
the user. The watchdog timer, which has a TRR and TCN, uses a fixed prescaler value.
The timer features are as follows:
Two general-purpose timer units:
- maximum period of 16 seconds (at 16.67 MHz),
- 60-nanosecond resolution (at 16.67 MHz),
- programmable sources for the clock input,
- input capture capability,
- output compare with programmable mode for the output pin,
- free run and restart modes.
One watchdog timer with a 16-bit counter and a reference register:
- maximum period of 16 seconds (16.67 MHz),
- 0.5-millisecond resolution (at 16 MHz),
- output signal (WDOG),
- interrupt capability.
External Chip-select
Signals and Wait-state
Logic
The TS68302 has a set of four programmable chip-select signals. Each chip select has
an identical structure. For each memory area, an internally generated cycle-termination
signal (DTACK) may be defined with up to six wait states to avoid using board space for
cycle-termination logic. The four signals may each support four different classes of
memory, such as high-speed static RAM, slower dynamic RAM, EPROM, and nonvola-
tile RAM. The chip-select and wait-state generation logic is active for all potential bus
masters.
Clock Generator
The TS68302 has an on-chip clock generator which supplies internal and external high-
speed clocks (up to 16.67 MHz). The clock circuitry uses three dedicated pins: EXTAL,
XTAL, and CLKO.
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